Remove defines by duplicating end_of_instruction_cleanup.

src/trusted/validator_ragel/unreviewed/decoder_x86_64.rl

 /*
  * Copyright (c) 2011 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /*
  * Full-blown decoder for amd64 case.  Can be used to decode instruction
  * sequence and process it, but right now is only used in tests.
  *
@@ skipping 76 matching lines @@
     "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
   include relative_fields_decoder_actions
     "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
   include relative_fields_parsing
     "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
   include cpuid_actions
     "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
 
   include decode_x86_64 "decoder_x86_64_instruction.rl";
 
-  include decoder
-    "native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
+  action end_of_instruction_cleanup {
+    process_instruction(instruction_begin, current_position + 1, &instruction,
+                        userdata);
+    instruction_begin = current_position + 1;
+    SET_DISP_TYPE(DISPNONE);
+    SET_IMM_TYPE(IMMNONE);
+    SET_IMM2_TYPE(IMMNONE);
+    SET_REX_PREFIX(FALSE);
+    SET_DATA16_PREFIX(FALSE);
+    SET_LOCK_PREFIX(FALSE);
+    SET_REPNZ_PREFIX(FALSE);
+    SET_REPZ_PREFIX(FALSE);
+    SET_BRANCH_NOT_TAKEN(FALSE);
+    SET_BRANCH_TAKEN(FALSE);
+    /* Top three bis of VEX2 are inverted: see AMD/Intel manual.  */

[halyavin, 2013/03/15 10:59:38]

bis->bits

[halyavin, 2013/03/15 10:59:38]

+/* Pass VEX2 prefix value that corresponds to zero bits. */

[khim, 2013/03/15 11:03:21]

Done.

[khim, 2013/03/15 11:03:21]

Done.

+    SET_VEX_PREFIX2(VEX_R | VEX_X | VEX_B);
+    SET_VEX_PREFIX3(0x00);
+    SET_ATT_INSTRUCTION_SUFFIX(NULL);
+    CLEAR_SPURIOUS_REX_B();
+    CLEAR_SPURIOUS_REX_X();
+    CLEAR_SPURIOUS_REX_R();
+    CLEAR_SPURIOUS_REX_W();
+  }
 
-  main := decoder;
+  action report_fatal_error {
+    process_error(current_position, userdata);
+    result = FALSE;
+    goto error_detected;
+  }
+
+  decoder := (one_instruction @end_of_instruction_cleanup)*
+             $!report_fatal_error;
 }%%
 
 %% write data;
 
 int DecodeChunkAMD64(const uint8_t *data, size_t size,
                      ProcessInstructionFunc process_instruction,
                      ProcessDecodingErrorFunc process_error,
                      void *userdata) {
   const uint8_t *current_position = data;
   const uint8_t *end_of_data = data + size;
   const uint8_t *instruction_begin = current_position;
-  uint8_t vex_prefix2 = 0xe0;
+  /* Top three bis of VEX2 are inverted: see AMD/Intel manual.  */

[halyavin, 2013/03/15 10:59:38]

bis->bits

[khim, 2013/03/15 11:03:21]

Done.

+  uint8_t vex_prefix2 = VEX_R | VEX_X | VEX_B;
   uint8_t vex_prefix3 = 0x00;
   enum ImmediateMode imm_operand = IMMNONE;
   enum ImmediateMode imm2_operand = IMMNONE;
   struct Instruction instruction;
   int result = TRUE;
 
   int current_state;
 
-  SET_DISP_TYPE(DISPNONE);
-  SET_IMM_TYPE(IMMNONE);
-  SET_IMM2_TYPE(IMMNONE);
-  SET_REX_PREFIX(FALSE);
-  SET_DATA16_PREFIX(FALSE);
-  SET_LOCK_PREFIX(FALSE);
-  SET_REPNZ_PREFIX(FALSE);
-  SET_REPZ_PREFIX(FALSE);
-  SET_BRANCH_NOT_TAKEN(FALSE);
-  SET_BRANCH_TAKEN(FALSE);
-  SET_ATT_INSTRUCTION_SUFFIX(NULL);
-  instruction.prefix.rex_b_spurious = FALSE;
-  instruction.prefix.rex_x_spurious = FALSE;
-  instruction.prefix.rex_r_spurious = FALSE;
-  instruction.prefix.rex_w_spurious = FALSE;
+  memset(&instruction, 0, sizeof instruction);
 
   %% write init;
   %% write exec;
 
 error_detected:
   return result;
 }