Added a version of the v8::HandleScope constructor with an Isolate and use that consistently.

test/cctest/test-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 44 matching lines @@
     env = v8::Context::New();
   }
 }
 
 
 #define __ assm.
 
 
 TEST(MIPS0) {
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
 
   // Addition.
   __ addu(v0, a0, a1);
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(&desc);
   Object* code = HEAP->CreateCode(
       desc,
       Code::ComputeFlags(Code::STUB),
       Handle<Code>())->ToObjectChecked();
   CHECK(code->IsCode());
   F2 f = FUNCTION_CAST<F2>(Code::cast(code)->entry());
   int res = reinterpret_cast<int>(CALL_GENERATED_CODE(f, 0xab0, 0xc, 0, 0, 0));
   ::printf("f() = %d\n", res);
   CHECK_EQ(0xabc, res);
 }
 
 
 TEST(MIPS1) {
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
   Label L, C;
 
   __ mov(a1, a0);
   __ li(v0, 0);
   __ b(&C);
   __ nop();
 
   __ bind(&L);
   __ addu(v0, v0, a1);
   __ addiu(a1, a1, -1);
@@ skipping 15 matching lines @@
   CHECK(code->IsCode());
   F1 f = FUNCTION_CAST<F1>(Code::cast(code)->entry());
   int res = reinterpret_cast<int>(CALL_GENERATED_CODE(f, 50, 0, 0, 0, 0));
   ::printf("f() = %d\n", res);
   CHECK_EQ(1275, res);
 }
 
 
 TEST(MIPS2) {
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
 
   Label exit, error;
 
   // ----- Test all instructions.
 
   // Test lui, ori, and addiu, used in the li pseudo-instruction.
   // This way we can then safely load registers with chosen values.
 
   __ ori(t0, zero_reg, 0);
   __ lui(t0, 0x1234);
@@ skipping 118 matching lines @@
   F2 f = FUNCTION_CAST<F2>(Code::cast(code)->entry());
   int res = reinterpret_cast<int>(CALL_GENERATED_CODE(f, 0xab0, 0xc, 0, 0, 0));
   ::printf("f() = %d\n", res);
   CHECK_EQ(0x31415926, res);
 }
 
 
 TEST(MIPS3) {
   // Test floating point instructions.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     double a;
     double b;
     double c;
     double d;
     double e;
     double f;
     double g;
     double h;
     double i;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatureScope scope(&assm, FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ add_d(f8, f4, f6);
     __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, c)) );  // c = a + b.
 
@@ skipping 53 matching lines @@
     CHECK_EQ(120.44, t.f);
     CHECK_EQ(10.97451593465515908537, t.g);
     CHECK_EQ(6.875, t.h);
   }
 }
 
 
 TEST(MIPS4) {
   // Test moves between floating point and integer registers.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     double a;
     double b;
     double c;
   } T;
   T t;
 
-  Assembler assm(Isolate::Current(), NULL, 0);
+  Assembler assm(isolate, NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatureScope scope(&assm, FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
 
     // Swap f4 and f6, by using four integer registers, t0-t3.
     __ mfc1(t0, f4);
@@ skipping 30 matching lines @@
     CHECK_EQ(2.75e11, t.a);
     CHECK_EQ(2.75e11, t.b);
     CHECK_EQ(1.5e22, t.c);
   }
 }
 
 
 TEST(MIPS5) {
   // Test conversions between doubles and integers.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     double a;
     double b;
     int i;
     int j;
   } T;
   T t;
 
-  Assembler assm(Isolate::Current(), NULL, 0);
+  Assembler assm(isolate, NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatureScope scope(&assm, FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ lw(t0, MemOperand(a0, OFFSET_OF(T, i)) );
     __ lw(t1, MemOperand(a0, OFFSET_OF(T, j)) );
@@ skipping 40 matching lines @@
     CHECK_EQ(-100000.0, t.b);
     CHECK_EQ(15000, t.i);
     CHECK_EQ(275000000, t.j);
   }
 }
 
 
 TEST(MIPS6) {
   // Test simple memory loads and stores.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     uint32_t ui;
     int32_t si;
     int32_t r1;
     int32_t r2;
     int32_t r3;
     int32_t r4;
     int32_t r5;
     int32_t r6;
   } T;
   T t;
 
-  Assembler assm(Isolate::Current(), NULL, 0);
+  Assembler assm(isolate, NULL, 0);
   Label L, C;
 
   // Basic word load/store.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, ui)) );
   __ sw(t0, MemOperand(a0, OFFSET_OF(T, r1)) );
 
   // lh with positive data.
   __ lh(t1, MemOperand(a0, OFFSET_OF(T, ui)) );
   __ sw(t1, MemOperand(a0, OFFSET_OF(T, r2)) );
 
@@ skipping 37 matching lines @@
   CHECK_EQ(0xffffbbcc, t.r3);
   CHECK_EQ(0x0000bbcc, t.r4);
   CHECK_EQ(0xffffffcc, t.r5);
   CHECK_EQ(0x3333bbcc, t.r6);
 }
 
 
 TEST(MIPS7) {
   // Test floating point compare and branch instructions.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     double a;
     double b;
     double c;
     double d;
     double e;
     double f;
     int32_t result;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
   Label neither_is_nan, less_than, outa_here;
 
   if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatureScope scope(&assm, FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ c(UN, D, f4, f6);
     __ bc1f(&neither_is_nan);
     __ nop();
@@ skipping 45 matching lines @@
     CHECK_EQ(1.5e14, t.a);
     CHECK_EQ(2.75e11, t.b);
     CHECK_EQ(1, t.result);
   }
 }
 
 
 TEST(MIPS8) {
   // Test ROTR and ROTRV instructions.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     int32_t input;
     int32_t result_rotr_4;
     int32_t result_rotr_8;
     int32_t result_rotr_12;
     int32_t result_rotr_16;
     int32_t result_rotr_20;
     int32_t result_rotr_24;
     int32_t result_rotr_28;
     int32_t result_rotrv_4;
     int32_t result_rotrv_8;
     int32_t result_rotrv_12;
     int32_t result_rotrv_16;
     int32_t result_rotrv_20;
     int32_t result_rotrv_24;
     int32_t result_rotrv_28;
   } T;
   T t;
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
 
   // Basic word load.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, input)) );
 
   // ROTR instruction (called through the Ror macro).
   __ Ror(t1, t0, 0x0004);
   __ Ror(t2, t0, 0x0008);
   __ Ror(t3, t0, 0x000c);
   __ Ror(t4, t0, 0x0010);
   __ Ror(t5, t0, 0x0014);
@@ skipping 62 matching lines @@
   CHECK_EQ(0x56781234, t.result_rotrv_16);
   CHECK_EQ(0x45678123, t.result_rotrv_20);
   CHECK_EQ(0x34567812, t.result_rotrv_24);
   CHECK_EQ(0x23456781, t.result_rotrv_28);
 }
 
 
 TEST(MIPS9) {
   // Test BRANCH improvements.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
   Label exit, exit2, exit3;
 
   __ Branch(&exit, ge, a0, Operand(0x00000000));
   __ Branch(&exit2, ge, a0, Operand(0x00001FFF));
   __ Branch(&exit3, ge, a0, Operand(0x0001FFFF));
 
   __ bind(&exit);
   __ bind(&exit2);
   __ bind(&exit3);
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(&desc);
   Object* code = HEAP->CreateCode(
       desc,
       Code::ComputeFlags(Code::STUB),
       Handle<Code>())->ToObjectChecked();
   CHECK(code->IsCode());
 }
 
 
 TEST(MIPS10) {
   // Test conversions between doubles and long integers.
   // Test hos the long ints map to FP regs pairs.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     double a;
     double b;
     int32_t dbl_mant;
     int32_t dbl_exp;
     int32_t long_hi;
     int32_t long_lo;
     int32_t b_long_hi;
     int32_t b_long_lo;
   } T;
   T t;
 
-  Assembler assm(Isolate::Current(), NULL, 0);
+  Assembler assm(isolate, NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU) && kArchVariant == kMips32r2) {
     CpuFeatureScope scope(&assm, FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
 
     // Save the raw bits of the double.
     __ mfc1(t0, f0);
@@ skipping 39 matching lines @@
     CHECK_EQ(0x7fffffff, t.long_lo);
     // 0xFF00FF00FF -> 1.095233372415e12.
     CHECK_EQ(1.095233372415e12, t.b);
   }
 }
 
 
 TEST(MIPS11) {
   // Test LWL, LWR, SWL and SWR instructions.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     int32_t reg_init;
     int32_t mem_init;
     int32_t lwl_0;
     int32_t lwl_1;
     int32_t lwl_2;
     int32_t lwl_3;
     int32_t lwr_0;
     int32_t lwr_1;
     int32_t lwr_2;
     int32_t lwr_3;
     int32_t swl_0;
     int32_t swl_1;
     int32_t swl_2;
     int32_t swl_3;
     int32_t swr_0;
     int32_t swr_1;
     int32_t swr_2;
     int32_t swr_3;
   } T;
   T t;
 
-  Assembler assm(Isolate::Current(), NULL, 0);
+  Assembler assm(isolate, NULL, 0);
 
   // Test all combinations of LWL and vAddr.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, reg_init)) );
   __ lwl(t0, MemOperand(a0, OFFSET_OF(T, mem_init)) );
   __ sw(t0, MemOperand(a0, OFFSET_OF(T, lwl_0)) );
 
   __ lw(t1, MemOperand(a0, OFFSET_OF(T, reg_init)) );
   __ lwl(t1, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) );
   __ sw(t1, MemOperand(a0, OFFSET_OF(T, lwl_1)) );
 
@@ skipping 98 matching lines @@
 
   CHECK_EQ(0xaabbccdd, t.swr_0);
   CHECK_EQ(0xbbccdd44, t.swr_1);
   CHECK_EQ(0xccdd3344, t.swr_2);
   CHECK_EQ(0xdd223344, t.swr_3);
 }
 
 
 TEST(MIPS12) {
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
       int32_t  x;
       int32_t  y;
       int32_t  y1;
       int32_t  y2;
       int32_t  y3;
       int32_t  y4;
   } T;
   T t;
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
 
   __ mov(t6, fp);  // Save frame pointer.
   __ mov(fp, a0);  // Access struct T by fp.
   __ lw(t0, MemOperand(a0, OFFSET_OF(T, y)) );
   __ lw(t3, MemOperand(a0, OFFSET_OF(T, y4)) );
 
   __ addu(t1, t0, t3);
   __ subu(t4, t0, t3);
   __ nop();
   __ push(t0);  // These instructions disappear after opt.
@@ skipping 58 matching lines @@
   Object* dummy = CALL_GENERATED_CODE(f, &t, 0, 0, 0, 0);
   USE(dummy);
 
   CHECK_EQ(3, t.y1);
 }
 
 
 TEST(MIPS13) {
   // Test Cvt_d_uw and Trunc_uw_d macros.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
   typedef struct {
     double cvt_big_out;
     double cvt_small_out;
     uint32_t trunc_big_out;
     uint32_t trunc_small_out;
     uint32_t cvt_big_in;
     uint32_t cvt_small_in;
   } T;
   T t;
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
 
   if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatureScope scope(&assm, FPU);
 
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_small_in)));
     __ Cvt_d_uw(f10, t0, f22);
     __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, cvt_small_out)));
 
     __ Trunc_uw_d(f10, f10, f22);
     __ swc1(f10, MemOperand(a0, OFFSET_OF(T, trunc_small_out)));
@@ skipping 29 matching lines @@
     CHECK_EQ(static_cast<int>(t.trunc_big_out), static_cast<int>(t.cvt_big_in));
     CHECK_EQ(static_cast<int>(t.trunc_small_out),
              static_cast<int>(t.cvt_small_in));
   }
 }
 
 
 TEST(MIPS14) {
   // Test round, floor, ceil, trunc, cvt.
   InitializeVM();
-  v8::HandleScope scope;
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
 
 #define ROUND_STRUCT_ELEMENT(x) \
   int32_t x##_up_out; \
   int32_t x##_down_out; \
   int32_t neg_##x##_up_out; \
   int32_t neg_##x##_down_out; \
   uint32_t x##_err1_out; \
   uint32_t x##_err2_out; \
   uint32_t x##_err3_out; \
   uint32_t x##_err4_out; \
@@ skipping 12 matching lines @@
     ROUND_STRUCT_ELEMENT(round)
     ROUND_STRUCT_ELEMENT(floor)
     ROUND_STRUCT_ELEMENT(ceil)
     ROUND_STRUCT_ELEMENT(trunc)
     ROUND_STRUCT_ELEMENT(cvt)
   } T;
   T t;
 
 #undef ROUND_STRUCT_ELEMENT
 
-  MacroAssembler assm(Isolate::Current(), NULL, 0);
+  MacroAssembler assm(isolate, NULL, 0);
 
   if (CpuFeatures::IsSupported(FPU)) {
     CpuFeatureScope scope(&assm, FPU);
 
     // Save FCSR.
     __ cfc1(a1, FCSR);
     // Disable FPU exceptions.
     __ ctc1(zero_reg, FCSR);
 #define RUN_ROUND_TEST(x) \
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_up_in))); \
@@ skipping 82 matching lines @@
     CHECK_ROUND_RESULT(floor);
     CHECK_ROUND_RESULT(ceil);
     CHECK_ROUND_RESULT(cvt);
   }
 }
 
 
 TEST(MIPS15) {
   // Test chaining of label usages within instructions (issue 1644).
   InitializeVM();
-  v8::HandleScope scope;
-  Assembler assm(Isolate::Current(), NULL, 0);
+  Isolate* isolate = Isolate::Current();
+  HandleScope scope(isolate);
+  Assembler assm(isolate, NULL, 0);
 
   Label target;
   __ beq(v0, v1, &target);
   __ nop();
   __ bne(v0, v1, &target);
   __ nop();
   __ bind(&target);
   __ nop();
 }
 
 #undef __