Simplify constant pool usage in x64 code generator (by removing extra argument

runtime/vm/assembler_x64.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_X64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/heap.h"
 #include "vm/instructions.h"
 #include "vm/locations.h"
 #include "vm/memory_region.h"
 #include "vm/runtime_entry.h"
 #include "vm/stack_frame.h"
 #include "vm/stub_code.h"
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
 DECLARE_FLAG(bool, inline_alloc);
 
 
 Assembler::Assembler(bool use_far_branches)
     : buffer_(),
       prologue_offset_(-1),
       comments_(),
-      constant_pool_allowed_(true) {
+      constant_pool_allowed_(false) {
   // Far branching mode is only needed and implemented for MIPS and ARM.
   ASSERT(!use_far_branches);
 }
 
 
 void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
   memset(reinterpret_cast<void*>(data), Instr::kBreakPointInstruction, length);
 }
 
 
@@ skipping 17 matching lines @@
 void Assembler::call(Label* label) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   static const int kSize = 5;
   EmitUint8(0xE8);
   EmitLabel(label, kSize);
 }
 
 
 void Assembler::LoadExternalLabel(Register dst,
                                   const ExternalLabel* label,
-                                  Patchability patchable,
-                                  Register pp) {
+                                  Patchability patchable) {
   const int32_t offset = ObjectPool::element_offset(
       object_pool_wrapper_.FindExternalLabel(label, patchable));
-  LoadWordFromPoolOffset(dst, pp, offset - kHeapObjectTag);
+  LoadWordFromPoolOffset(dst, offset - kHeapObjectTag);
 }
 
 
 void Assembler::call(const ExternalLabel* label) {
   {  // Encode movq(TMP, Immediate(label->address())), but always as imm64.
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(TMP, REX_W);
     EmitUint8(0xB8 | (TMP & 7));
     EmitInt64(label->address());
   }
   call(TMP);
 }
 
 
 void Assembler::CallPatchable(const ExternalLabel* label) {
   ASSERT(constant_pool_allowed());
   intptr_t call_start = buffer_.GetPosition();
   const int32_t offset = ObjectPool::element_offset(
       object_pool_wrapper_.FindExternalLabel(label, kPatchable));
   call(Address::AddressBaseImm32(PP, offset - kHeapObjectTag));
   ASSERT((buffer_.GetPosition() - call_start) == kCallExternalLabelSize);
 }
 
 
-void Assembler::Call(const ExternalLabel* label, Register pp) {
+void Assembler::Call(const ExternalLabel* label) {
+  ASSERT(constant_pool_allowed());
   const int32_t offset = ObjectPool::element_offset(
       object_pool_wrapper_.FindExternalLabel(label, kNotPatchable));
-  call(Address::AddressBaseImm32(pp, offset - kHeapObjectTag));
+  call(Address::AddressBaseImm32(PP, offset - kHeapObjectTag));
 }
 
 
 void Assembler::pushq(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(reg, REX_NONE);
   EmitUint8(0x50 | (reg & 7));
 }
 
 
@@ skipping 10 matching lines @@
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitUint8(0x68);
     EmitImmediate(imm);
   } else {
     movq(TMP, imm);
     pushq(TMP);
   }
 }
 
 
-void Assembler::PushImmediate(const Immediate& imm, Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
-    LoadImmediate(TMP, imm, pp);
+void Assembler::PushImmediate(const Immediate& imm) {
+  if (imm.is_int32()) {
+    pushq(imm);
+  } else {
+    LoadImmediate(TMP, imm);
     pushq(TMP);
-  } else {
-    pushq(imm);
   }
 }
 
 
 void Assembler::popq(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitRegisterREX(reg, REX_NONE);
   EmitUint8(0x58 | (reg & 7));
 }
 
@@ skipping 630 matching lines @@
 
 void Assembler::notps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
   } float_not_constant =
       { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
   LoadImmediate(
-      TMP, Immediate(reinterpret_cast<intptr_t>(&float_not_constant)), PP);
+      TMP, Immediate(reinterpret_cast<intptr_t>(&float_not_constant)));
   xorps(dst, Address(TMP, 0));
 }
 
 
 void Assembler::negateps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
   } float_negate_constant =
       { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
   LoadImmediate(
-      TMP, Immediate(reinterpret_cast<intptr_t>(&float_negate_constant)), PP);
+      TMP, Immediate(reinterpret_cast<intptr_t>(&float_negate_constant)));
   xorps(dst, Address(TMP, 0));
 }
 
 
 void Assembler::absps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
   } float_absolute_constant =
       { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF };
   LoadImmediate(
-      TMP, Immediate(reinterpret_cast<intptr_t>(&float_absolute_constant)), PP);
+      TMP, Immediate(reinterpret_cast<intptr_t>(&float_absolute_constant)));
   andps(dst, Address(TMP, 0));
 }
 
 
 void Assembler::zerowps(XmmRegister dst) {
   static const struct ALIGN16 {
     uint32_t a;
     uint32_t b;
     uint32_t c;
     uint32_t d;
   } float_zerow_constant =
       { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 };
   LoadImmediate(
-      TMP, Immediate(reinterpret_cast<intptr_t>(&float_zerow_constant)), PP);
+      TMP, Immediate(reinterpret_cast<intptr_t>(&float_zerow_constant)));
   andps(dst, Address(TMP, 0));
 }
 
 
 void Assembler::cmppseq(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitREX_RB(dst, src);
   EmitUint8(0x0F);
   EmitUint8(0xC2);
   EmitXmmRegisterOperand(dst & 7, src);
@@ skipping 167 matching lines @@
 }
 
 
 void Assembler::negatepd(XmmRegister dst) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
   } double_negate_constant =
       { 0x8000000000000000LL, 0x8000000000000000LL };
   LoadImmediate(
-      TMP, Immediate(reinterpret_cast<intptr_t>(&double_negate_constant)), PP);
+      TMP, Immediate(reinterpret_cast<intptr_t>(&double_negate_constant)));
   xorpd(dst, Address(TMP, 0));
 }
 
 
 void Assembler::subpd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   ASSERT(src <= XMM15);
   ASSERT(dst <= XMM15);
   EmitUint8(0x66);
   EmitREX_RB(dst, src);
@@ skipping 27 matching lines @@
 }
 
 
 void Assembler::abspd(XmmRegister dst) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
   } double_absolute_const =
       { 0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL };
   LoadImmediate(
-      TMP, Immediate(reinterpret_cast<intptr_t>(&double_absolute_const)), PP);
+      TMP, Immediate(reinterpret_cast<intptr_t>(&double_absolute_const)));
   andpd(dst, Address(TMP, 0));
 }
 
 
 void Assembler::minpd(XmmRegister dst, XmmRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   ASSERT(src <= XMM15);
   ASSERT(dst <= XMM15);
   EmitUint8(0x66);
   EmitREX_RB(dst, src);
@@ skipping 392 matching lines @@
   }
 }
 
 
 void Assembler::cmpq(Register reg, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(reg, REX_W);
     EmitComplex(7, Operand(reg), imm);
   } else {
+    ASSERT(reg != TMP);
     movq(TMP, imm);
     cmpq(reg, TMP);
   }
 }
 
 
 void Assembler::cmpq(Register reg0, Register reg1) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(reg1);
   EmitOperandREX(reg0, operand, REX_W);
   EmitUint8(0x3B);
   EmitOperand(reg0 & 7, operand);
 }
 
 
 void Assembler::cmpq(Register reg, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(reg, address, REX_W);
   EmitUint8(0x3B);
   EmitOperand(reg & 7, address);
 }
 
 
-void Assembler::CompareImmediate(Register reg, const Immediate& imm,
-                                 Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
-    LoadImmediate(TMP, imm, pp);
+void Assembler::CompareImmediate(Register reg, const Immediate& imm) {
+  if (imm.is_int32()) {
+    cmpq(reg, imm);
+  } else {
+    ASSERT(reg != TMP);
+    LoadImmediate(TMP, imm);
     cmpq(reg, TMP);
-  } else {
-    cmpq(reg, imm);
   }
 }
 
 
-void Assembler::CompareImmediate(const Address& address, const Immediate& imm,
-                                 Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
-    LoadImmediate(TMP, imm, pp);
+void Assembler::CompareImmediate(const Address& address, const Immediate& imm) {
+  if (imm.is_int32()) {
+    cmpq(address, imm);
+  } else {
+    LoadImmediate(TMP, imm);
     cmpq(address, TMP);
-  } else {
-    cmpq(address, imm);
   }
 }
 
 
 void Assembler::testl(Register reg1, Register reg2) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(reg2);
   EmitOperandREX(reg1, operand, REX_NONE);
   EmitUint8(0x85);
   EmitOperand(reg1 & 7, operand);
@@ skipping 74 matching lines @@
     } else {
       EmitRegisterREX(reg, REX_W);
       EmitUint8(0xF7);
       EmitUint8(0xC0 | (reg & 7));
     }
     EmitImmediate(imm);
   }
 }
 
 
-void Assembler::TestImmediate(Register dst, const Immediate& imm, Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
+void Assembler::TestImmediate(Register dst, const Immediate& imm) {
+  if (imm.is_int32()) {
+    testq(dst, imm);
+  } else {
     ASSERT(dst != TMP);
-    LoadImmediate(TMP, imm, pp);
+    LoadImmediate(TMP, imm);
     testq(dst, TMP);
-  } else {
-    testq(dst, imm);
   }
 }
 
 
 void Assembler::andl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x23);
   EmitOperand(dst & 7, operand);
@@ skipping 56 matching lines @@
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::andq(Register dst, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(dst, REX_W);
     EmitComplex(4, Operand(dst), imm);
   } else {
+    ASSERT(dst != TMP);
     movq(TMP, imm);
     andq(dst, TMP);
   }
 }
 
 
-void Assembler::AndImmediate(Register dst, const Immediate& imm, Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
+void Assembler::AndImmediate(Register dst, const Immediate& imm) {
+  if (imm.is_int32()) {
+    andq(dst, imm);
+  } else {
     ASSERT(dst != TMP);
-    LoadImmediate(TMP, imm, pp);
+    LoadImmediate(TMP, imm);
     andq(dst, TMP);
-  } else {
-    andq(dst, imm);
   }
 }
 
 
 void Assembler::orq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x0B);
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::orq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x0B);
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::orq(Register dst, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(dst, REX_W);
     EmitComplex(1, Operand(dst), imm);
   } else {
+    ASSERT(dst != TMP);
     movq(TMP, imm);
     orq(dst, TMP);
   }
 }
 
 
-void Assembler::OrImmediate(Register dst, const Immediate& imm, Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
+void Assembler::OrImmediate(Register dst, const Immediate& imm) {
+  if (imm.is_int32()) {
+    orq(dst, imm);
+  } else {
     ASSERT(dst != TMP);
-    LoadImmediate(TMP, imm, pp);
+    LoadImmediate(TMP, imm);
     orq(dst, TMP);
-  } else {
-    orq(dst, imm);
   }
 }
 
 
 void Assembler::xorq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_W);
   EmitUint8(0x33);
   EmitOperand(dst & 7, operand);
@@ skipping 15 matching lines @@
   EmitOperand(src & 7, dst);
 }
 
 
 void Assembler::xorq(Register dst, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(dst, REX_W);
     EmitComplex(6, Operand(dst), imm);
   } else {
+    ASSERT(dst != TMP);
     movq(TMP, imm);
     xorq(dst, TMP);
   }
 }
 
 
-void Assembler::XorImmediate(Register dst, const Immediate& imm, Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
+void Assembler::XorImmediate(Register dst, const Immediate& imm) {
+  if (imm.is_int32()) {
+    xorq(dst, imm);
+  } else {
     ASSERT(dst != TMP);
-    LoadImmediate(TMP, imm, pp);
+    LoadImmediate(TMP, imm);
     xorq(dst, TMP);
-  } else {
-    xorq(dst, imm);
   }
 }
 
 
 void Assembler::addl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
   EmitOperandREX(dst, operand, REX_NONE);
   EmitUint8(0x03);
   EmitOperand(dst & 7, operand);
@@ skipping 65 matching lines @@
   EmitOperand(dst & 7, address);
 }
 
 
 void Assembler::addq(Register dst, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(dst, REX_W);
     EmitComplex(0, Operand(dst), imm);
   } else {
+    ASSERT(dst != TMP);
     movq(TMP, imm);
     addq(dst, TMP);
   }
 }
 
 
 void Assembler::addq(const Address& address, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitOperandREX(0, address, REX_W);
@@ skipping 21 matching lines @@
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::adcq(Register dst, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(dst, REX_W);
     EmitComplex(2, Operand(dst), imm);
   } else {
+    ASSERT(dst != TMP);
     movq(TMP, imm);
     adcq(dst, TMP);
   }
 }
 
 
 void Assembler::adcq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x13);
@@ skipping 136 matching lines @@
 
 void Assembler::imulq(Register reg, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     Operand operand(reg);
     EmitOperandREX(reg, operand, REX_W);
     EmitUint8(0x69);
     EmitOperand(reg & 7, Operand(reg));
     EmitImmediate(imm);
   } else {
+    ASSERT(reg != TMP);
     movq(TMP, imm);
     imulq(reg, TMP);
   }
 }
 
 
-void Assembler::MulImmediate(Register reg, const Immediate& imm, Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
+void Assembler::MulImmediate(Register reg, const Immediate& imm) {
+  if (imm.is_int32()) {
+    imulq(reg, imm);
+  } else {
     ASSERT(reg != TMP);
-    LoadImmediate(TMP, imm, pp);
+    LoadImmediate(TMP, imm);
     imulq(reg, TMP);
-  } else {
-    imulq(reg, imm);
   }
 }
 
 
 void Assembler::imulq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x0F);
   EmitUint8(0xAF);
   EmitOperand(dst & 7, address);
@@ skipping 16 matching lines @@
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::subq(Register reg, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(reg, REX_W);
     EmitComplex(5, Operand(reg), imm);
   } else {
+    ASSERT(reg != TMP);
     movq(TMP, imm);
     subq(reg, TMP);
   }
 }
 
 
 void Assembler::subq(Register reg, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(reg, address, REX_W);
   EmitUint8(0x2B);
@@ skipping 29 matching lines @@
   EmitOperand(dst & 7, operand);
 }
 
 
 void Assembler::sbbq(Register dst, const Immediate& imm) {
   if (imm.is_int32()) {
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(dst, REX_W);
     EmitComplex(3, Operand(dst), imm);
   } else {
+    ASSERT(dst != TMP);
     movq(TMP, imm);
     sbbq(dst, TMP);
   }
 }
 
 
 void Assembler::sbbq(Register dst, const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitOperandREX(dst, address, REX_W);
   EmitUint8(0x1B);
@@ skipping 407 matching lines @@
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     EmitRegisterREX(TMP, REX_W);
     EmitUint8(0xB8 | (TMP & 7));
     EmitInt64(label->address());
   }
   jmp(TMP);
 }
 
 
 void Assembler::JmpPatchable(const ExternalLabel* label, Register pp) {
-  ASSERT(constant_pool_allowed());
+  ASSERT((pp != PP) || constant_pool_allowed());
   intptr_t call_start = buffer_.GetPosition();
   const int32_t offset = ObjectPool::element_offset(
       object_pool_wrapper_.FindExternalLabel(label, kPatchable));
   // Patchable jumps always use a 32-bit immediate encoding.
   jmp(Address::AddressBaseImm32(pp, offset - kHeapObjectTag));
   ASSERT((buffer_.GetPosition() - call_start) == JumpPattern::kLengthInBytes);
 }
 
 
 void Assembler::Jmp(const ExternalLabel* label, Register pp) {
+  ASSERT((pp != PP) || constant_pool_allowed());
   const int32_t offset = ObjectPool::element_offset(
       object_pool_wrapper_.FindExternalLabel(label, kNotPatchable));
   jmp(Address(pp, offset - kHeapObjectTag));
 }
 
 
 void Assembler::lock() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xF0);
 }
@@ skipping 34 matching lines @@
     movq(to, from);
   }
 }
 
 
 void Assembler::PopRegister(Register r) {
   popq(r);
 }
 
 
-void Assembler::AddImmediate(Register reg, const Immediate& imm, Register pp) {
+void Assembler::AddImmediate(Register reg, const Immediate& imm) {
   const int64_t value = imm.value();
   if (value == 0) {
     return;
   }
   if ((value > 0) || (value == kMinInt64)) {
     if (value == 1) {
       incq(reg);
     } else {
-      if (CanLoadImmediateFromPool(imm, pp)) {
+      if (imm.is_int32()) {
+        addq(reg, imm);
+      } else {
         ASSERT(reg != TMP);
-        LoadImmediate(TMP, imm, pp);
+        LoadImmediate(TMP, imm);
         addq(reg, TMP);
-      } else {
-        addq(reg, imm);
       }
     }
   } else {
-    SubImmediate(reg, Immediate(-value), pp);
+    SubImmediate(reg, Immediate(-value));
   }
 }
 
 
-void Assembler::AddImmediate(const Address& address, const Immediate& imm,
-                             Register pp) {
+void Assembler::AddImmediate(const Address& address, const Immediate& imm) {
   const int64_t value = imm.value();
   if (value == 0) {
     return;
   }
   if ((value > 0) || (value == kMinInt64)) {
     if (value == 1) {
       incq(address);
     } else {
-      if (CanLoadImmediateFromPool(imm, pp)) {
-        LoadImmediate(TMP, imm, pp);
+      if (imm.is_int32()) {
+        addq(address, imm);
+      } else {
+        LoadImmediate(TMP, imm);
         addq(address, TMP);
-      } else {
-        addq(address, imm);
       }
     }
   } else {
-    SubImmediate(address, Immediate(-value), pp);
+    SubImmediate(address, Immediate(-value));
   }
 }
 
 
-void Assembler::SubImmediate(Register reg, const Immediate& imm, Register pp) {
+void Assembler::SubImmediate(Register reg, const Immediate& imm) {
   const int64_t value = imm.value();
   if (value == 0) {
     return;
   }
   if ((value > 0) || (value == kMinInt64)) {
     if (value == 1) {
       decq(reg);
     } else {
-      if (CanLoadImmediateFromPool(imm, pp)) {
+      if (imm.is_int32()) {
+        subq(reg, imm);
+      } else {
         ASSERT(reg != TMP);
-        LoadImmediate(TMP, imm, pp);
+        LoadImmediate(TMP, imm);
         subq(reg, TMP);
-      } else {
-        subq(reg, imm);
       }
     }
   } else {
-    AddImmediate(reg, Immediate(-value), pp);
+    AddImmediate(reg, Immediate(-value));
   }
 }
 
 
-void Assembler::SubImmediate(const Address& address, const Immediate& imm,
-                             Register pp) {
+void Assembler::SubImmediate(const Address& address, const Immediate& imm) {
   const int64_t value = imm.value();
   if (value == 0) {
     return;
   }
   if ((value > 0) || (value == kMinInt64)) {
     if (value == 1) {
       decq(address);
     } else {
-      if (CanLoadImmediateFromPool(imm, pp)) {
-        LoadImmediate(TMP, imm, pp);
+      if (imm.is_int32()) {
+        subq(address, imm);
+      } else {
+        LoadImmediate(TMP, imm);
         subq(address, TMP);
-      } else {
-        subq(address, imm);
       }
     }
   } else {
-    AddImmediate(address, Immediate(-value), pp);
+    AddImmediate(address, Immediate(-value));
   }
 }
 
 
 void Assembler::Drop(intptr_t stack_elements, Register tmp) {
   ASSERT(stack_elements >= 0);
   if (stack_elements <= 4) {
     for (intptr_t i = 0; i < stack_elements; i++) {
       popq(tmp);
     }
@@ skipping 15 matching lines @@
     // If the raw smi does not fit into a 32-bit signed int, then we'll keep
     // the raw value in the object pool.
     return !Utils::IsInt(32, reinterpret_cast<int64_t>(object.raw()));
   }
   ASSERT(object.IsNotTemporaryScopedHandle());
   ASSERT(object.IsOld());
   return true;
 }
 
 
-void Assembler::LoadWordFromPoolOffset(Register dst, Register pp,
-                                       int32_t offset) {
+void Assembler::LoadWordFromPoolOffset(Register dst, int32_t offset) {
+  ASSERT(constant_pool_allowed());
+  ASSERT(dst != PP);
   // This sequence must be of fixed size. AddressBaseImm32
   // forces the address operand to use a fixed-size imm32 encoding.
-  movq(dst, Address::AddressBaseImm32(pp, offset));
+  movq(dst, Address::AddressBaseImm32(PP, offset));
 }
 
 
 void Assembler::LoadIsolate(Register dst) {
   movq(dst, Address(THR, Thread::isolate_offset()));
 }
 
 
 void Assembler::LoadObjectHelper(Register dst,
                                  const Object& object,
-                                 Register pp,
                                  bool is_unique) {
   if (Thread::CanLoadFromThread(object)) {
     movq(dst, Address(THR, Thread::OffsetFromThread(object)));
   } else if (CanLoadFromObjectPool(object)) {
     const int32_t offset = ObjectPool::element_offset(
         is_unique ? object_pool_wrapper_.AddObject(object)
                   : object_pool_wrapper_.FindObject(object));
-    LoadWordFromPoolOffset(dst, pp, offset - kHeapObjectTag);
+    LoadWordFromPoolOffset(dst, offset - kHeapObjectTag);
   } else {
     ASSERT(object.IsSmi() || object.InVMHeap());
-    LoadImmediate(dst, Immediate(reinterpret_cast<int64_t>(object.raw())), pp);
+    LoadImmediate(dst, Immediate(reinterpret_cast<int64_t>(object.raw())));
   }
 }
 
 
-void Assembler::LoadObject(Register dst, const Object& object, Register pp) {
-  LoadObjectHelper(dst, object, pp, false);
+void Assembler::LoadFunctionFromCalleePool(Register dst,
+                                           const Function& function,
+                                           Register new_pp) {
+  ASSERT(!constant_pool_allowed());
+  ASSERT(new_pp != PP);
+  const int32_t offset =
+      ObjectPool::element_offset(object_pool_wrapper_.FindObject(function));
+  movq(dst, Address::AddressBaseImm32(new_pp, offset - kHeapObjectTag));
 }
 
 
-void Assembler::LoadUniqueObject(Register dst,
-                                 const Object& object,
-                                 Register pp) {
-  LoadObjectHelper(dst, object, pp, true);
+void Assembler::LoadObject(Register dst, const Object& object) {
+  LoadObjectHelper(dst, object, false);
 }
 
 
-void Assembler::StoreObject(const Address& dst, const Object& object,
-                            Register pp) {
+void Assembler::LoadUniqueObject(Register dst, const Object& object) {
+  LoadObjectHelper(dst, object, true);
+}
+
+
+void Assembler::StoreObject(const Address& dst, const Object& object) {
   if (Thread::CanLoadFromThread(object)) {
     movq(TMP, Address(THR, Thread::OffsetFromThread(object)));
     movq(dst, TMP);
   } else if (CanLoadFromObjectPool(object)) {
-    LoadObject(TMP, object, pp);
+    LoadObject(TMP, object);
     movq(dst, TMP);
   } else {
-    MoveImmediate(dst, Immediate(reinterpret_cast<int64_t>(object.raw())), pp);
+    MoveImmediate(dst, Immediate(reinterpret_cast<int64_t>(object.raw())));
   }
 }
 
 
-void Assembler::PushObject(const Object& object, Register pp) {
+void Assembler::PushObject(const Object& object) {
   if (Thread::CanLoadFromThread(object)) {
     pushq(Address(THR, Thread::OffsetFromThread(object)));
   } else if (CanLoadFromObjectPool(object)) {
-    LoadObject(TMP, object, pp);
+    LoadObject(TMP, object);
     pushq(TMP);
   } else {
-    PushImmediate(Immediate(reinterpret_cast<int64_t>(object.raw())), pp);
+    PushImmediate(Immediate(reinterpret_cast<int64_t>(object.raw())));
   }
 }
 
 
-void Assembler::CompareObject(Register reg, const Object& object, Register pp) {
+void Assembler::CompareObject(Register reg, const Object& object) {
   if (Thread::CanLoadFromThread(object)) {
     cmpq(reg, Address(THR, Thread::OffsetFromThread(object)));
   } else if (CanLoadFromObjectPool(object)) {
     const int32_t offset =
         ObjectPool::element_offset(object_pool_wrapper_.FindObject(object));
-    cmpq(reg, Address(pp, offset-kHeapObjectTag));
+    cmpq(reg, Address(PP, offset-kHeapObjectTag));
   } else {
     CompareImmediate(
-        reg, Immediate(reinterpret_cast<int64_t>(object.raw())), pp);
+        reg, Immediate(reinterpret_cast<int64_t>(object.raw())));
   }
 }
 
 
 intptr_t Assembler::FindImmediate(int64_t imm) {
   return object_pool_wrapper_.FindImmediate(imm);
 }
 
 
-bool Assembler::CanLoadImmediateFromPool(const Immediate& imm, Register pp) {
-  if (!constant_pool_allowed()) {
-    return false;
-  }
-  return !imm.is_int32() && (pp != kNoRegister);
-}
-
-
-void Assembler::LoadImmediate(Register reg, const Immediate& imm, Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
+void Assembler::LoadImmediate(Register reg, const Immediate& imm) {
+  if (imm.is_int32() || !constant_pool_allowed()) {
+    movq(reg, imm);
+  } else {
     int32_t offset = ObjectPool::element_offset(FindImmediate(imm.value()));
-    LoadWordFromPoolOffset(reg, pp, offset - kHeapObjectTag);
-  } else {
-    movq(reg, imm);
+    LoadWordFromPoolOffset(reg, offset - kHeapObjectTag);
   }
 }
 
 
-void Assembler::MoveImmediate(const Address& dst, const Immediate& imm,
-                              Register pp) {
-  if (CanLoadImmediateFromPool(imm, pp)) {
-    LoadImmediate(TMP, imm, pp);
+void Assembler::MoveImmediate(const Address& dst, const Immediate& imm) {
+  if (imm.is_int32()) {
+    movq(dst, imm);
+  } else {
+    LoadImmediate(TMP, imm);
     movq(dst, TMP);
-  } else {
-    movq(dst, imm);
   }
 }
 
 
 // Destroys the value register.
 void Assembler::StoreIntoObjectFilterNoSmi(Register object,
                                            Register value,
                                            Label* no_update) {
   COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
                  (kOldObjectAlignmentOffset == 0));
@@ skipping 165 matching lines @@
   Bind(&done);
   popq(value);
 #endif  // defined(DEBUG)
   // No store buffer update.
 }
 
 
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          const Object& value,
-                                         Register pp,
                                          FieldContent old_content) {
   VerifyHeapWord(dest, old_content);
   if (VerifiedMemory::enabled()) {
-    Register temp = (pp == RCX) ? RDX : RCX;
+    const Register temp = RCX;
     pushq(temp);
     leaq(temp, dest);
-    StoreObject(Address(temp, 0), value, pp);
-    StoreObject(Address(temp, VerifiedMemory::offset()), value, pp);
+    StoreObject(Address(temp, 0), value);
+    StoreObject(Address(temp, VerifiedMemory::offset()), value);
     popq(temp);
   } else {
-    StoreObject(dest, value, pp);
+    StoreObject(dest, value);
   }
   // TODO(koda): Use 'object', verify that generational barrier's not needed.
 }
 
 
 void Assembler::StoreIntoSmiField(const Address& dest, Register value) {
 #if defined(DEBUG)
   Label done;
   testq(value, Immediate(kHeapObjectTag));
   j(ZERO, &done);
@@ skipping 36 matching lines @@
 }
 
 
 void Assembler::DoubleNegate(XmmRegister d) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
   } double_negate_constant =
       {0x8000000000000000LL, 0x8000000000000000LL};
   LoadImmediate(
-      TMP, Immediate(reinterpret_cast<intptr_t>(&double_negate_constant)), PP);
+      TMP, Immediate(reinterpret_cast<intptr_t>(&double_negate_constant)));
   xorpd(d, Address(TMP, 0));
 }
 
 
 void Assembler::DoubleAbs(XmmRegister reg) {
   static const struct ALIGN16 {
     uint64_t a;
     uint64_t b;
   } double_abs_constant =
       {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL};
   LoadImmediate(TMP,
-      Immediate(reinterpret_cast<intptr_t>(&double_abs_constant)), PP);
+      Immediate(reinterpret_cast<intptr_t>(&double_abs_constant)));
   andpd(reg, Address(TMP, 0));
 }
 
 
 void Assembler::Stop(const char* message, bool fixed_length_encoding) {
   int64_t message_address = reinterpret_cast<int64_t>(message);
   if (FLAG_print_stop_message) {
     pushq(TMP);  // Preserve TMP register.
     pushq(RDI);  // Preserve RDI register.
     if (fixed_length_encoding) {
       AssemblerBuffer::EnsureCapacity ensured(&buffer_);
       EmitRegisterREX(RDI, REX_W);
       EmitUint8(0xB8 | (RDI & 7));
       EmitInt64(message_address);
     } else {
-      LoadImmediate(RDI, Immediate(message_address), PP);
+      LoadImmediate(RDI, Immediate(message_address));
     }
     call(&StubCode::PrintStopMessageLabel());
     popq(RDI);  // Restore RDI register.
     popq(TMP);  // Restore TMP register.
   } else {
     // Emit the lower half and the higher half of the message address as
     // immediate operands in the test rax instructions.
     testl(RAX, Immediate(Utils::Low32Bits(message_address)));
     testl(RAX, Immediate(Utils::High32Bits(message_address)));
   }
@@ skipping 57 matching lines @@
   if (OS::ActivationFrameAlignment() > 1) {
     andq(RSP, Immediate(~(OS::ActivationFrameAlignment() - 1)));
   }
 }
 
 
 void Assembler::PushRegisters(intptr_t cpu_register_set,
                               intptr_t xmm_register_set) {
   const intptr_t xmm_regs_count = RegisterSet::RegisterCount(xmm_register_set);
   if (xmm_regs_count > 0) {
-    AddImmediate(RSP, Immediate(-xmm_regs_count * kFpuRegisterSize), PP);
+    AddImmediate(RSP, Immediate(-xmm_regs_count * kFpuRegisterSize));
     // Store XMM registers with the lowest register number at the lowest
     // address.
     intptr_t offset = 0;
     for (intptr_t reg_idx = 0; reg_idx < kNumberOfXmmRegisters; ++reg_idx) {
       XmmRegister xmm_reg = static_cast<XmmRegister>(reg_idx);
       if (RegisterSet::Contains(xmm_register_set, xmm_reg)) {
         movups(Address(RSP, offset), xmm_reg);
         offset += kFpuRegisterSize;
       }
     }
@@ skipping 28 matching lines @@
     // XMM registers have the lowest register number at the lowest address.
     intptr_t offset = 0;
     for (intptr_t reg_idx = 0; reg_idx < kNumberOfXmmRegisters; ++reg_idx) {
       XmmRegister xmm_reg = static_cast<XmmRegister>(reg_idx);
       if (RegisterSet::Contains(xmm_register_set, xmm_reg)) {
         movups(xmm_reg, Address(RSP, offset));
         offset += kFpuRegisterSize;
       }
     }
     ASSERT(offset == (xmm_regs_count * kFpuRegisterSize));
-    AddImmediate(RSP, Immediate(offset), PP);
+    AddImmediate(RSP, Immediate(offset));
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   EnterFrame(0);
 
   // TODO(vegorov): avoid saving FpuTMP, it is used only as scratch.
   PushRegisters(CallingConventions::kVolatileCpuRegisters,
                 CallingConventions::kVolatileXmmRegisters);
@@ skipping 49 matching lines @@
 
 void Assembler::LoadPoolPointer(Register pp) {
   // Load new pool pointer.
   const intptr_t kRIPRelativeMovqSize = 7;
   const intptr_t entry_to_rip_offset = CodeSize() + kRIPRelativeMovqSize;
   const intptr_t object_pool_pc_dist =
       Instructions::HeaderSize() - Instructions::object_pool_offset();
   movq(pp, Address::AddressRIPRelative(
       -entry_to_rip_offset - object_pool_pc_dist));
   ASSERT(CodeSize() == entry_to_rip_offset);
+  set_constant_pool_allowed(pp == PP);
 }
 
 
 void Assembler::EnterDartFrameWithInfo(intptr_t frame_size,
                                        Register new_pp,
                                        Register pc_marker_override) {
+  ASSERT(!constant_pool_allowed());
   EnterFrame(0);
   pushq(pc_marker_override);
   pushq(PP);
   movq(PP, new_pp);
+  set_constant_pool_allowed(true);
   if (frame_size != 0) {
     subq(RSP, Immediate(frame_size));
   }
 }
 
 
 void Assembler::LeaveDartFrame() {
+  // LeaveDartFrame is called from stubs (pp disallowed) and from Dart code (pp
+  // allowed), so there is no point in checking the current value of
+  // constant_pool_allowed().
+  set_constant_pool_allowed(false);
   // Restore caller's PP register that was pushed in EnterDartFrame.
   movq(PP, Address(RBP, (kSavedCallerPpSlotFromFp * kWordSize)));
   LeaveFrame();
 }
 
 
 // On entry to a function compiled for OSR, the caller's frame pointer, the
 // stack locals, and any copied parameters are already in place.  The frame
 // pointer is already set up.  The PC marker is not correct for the
 // optimized function and there may be extra space for spill slots to
 // allocate.
 void Assembler::EnterOsrFrame(intptr_t extra_size,
                               Register new_pp,
                               Register pc_marker_override) {
+  ASSERT(!constant_pool_allowed());
   if (prologue_offset_ == -1) {
     Comment("PrologueOffset = %" Pd "", CodeSize());
     prologue_offset_ = CodeSize();
   }
   movq(Address(RBP, kPcMarkerSlotFromFp * kWordSize), pc_marker_override);
   movq(PP, new_pp);
+  set_constant_pool_allowed(true);
   if (extra_size != 0) {
     subq(RSP, Immediate(extra_size));
   }
 }
 
 
 void Assembler::EnterStubFrame() {
+  set_constant_pool_allowed(false);
   EnterFrame(0);
   pushq(Immediate(0));  // Push 0 in the saved PC area for stub frames.
   pushq(PP);  // Save caller's pool pointer
-  LoadPoolPointer(PP);
+  LoadPoolPointer();
 }
 
 
 void Assembler::LeaveStubFrame() {
+  set_constant_pool_allowed(false);
   // Restore caller's PP register that was pushed in EnterStubFrame.
   movq(PP, Address(RBP, (kSavedCallerPpSlotFromFp * kWordSize)));
   LeaveFrame();
 }
 
 
 void Assembler::MaybeTraceAllocation(intptr_t cid,
                                      Label* trace,
                                      bool near_jump,
                                      bool inline_isolate) {
@@ skipping 71 matching lines @@
   UpdateAllocationStats(cid, space, inline_isolate);
   Register temp_reg = TMP;
   intptr_t size_offset = ClassTable::SizeOffsetFor(cid, space == Heap::kNew);
   addq(Address(temp_reg, size_offset), Immediate(size_in_bytes));
 }
 
 
 void Assembler::TryAllocate(const Class& cls,
                             Label* failure,
                             bool near_jump,
-                            Register instance_reg,
-                            Register pp) {
+                            Register instance_reg) {
   ASSERT(failure != NULL);
   if (FLAG_inline_alloc) {
     // If this allocation is traced, program will jump to failure path
     // (i.e. the allocation stub) which will allocate the object and trace the
     // allocation call site.
     MaybeTraceAllocation(cls.id(), failure, near_jump);
     Heap* heap = Isolate::Current()->heap();
     const intptr_t instance_size = cls.instance_size();
     Heap::Space space = heap->SpaceForAllocation(cls.id());
-    LoadImmediate(TMP, Immediate(heap->TopAddress(space)), pp);
+    LoadImmediate(TMP, Immediate(heap->TopAddress(space)));
     movq(instance_reg, Address(TMP, 0));
-    AddImmediate(instance_reg, Immediate(instance_size), pp);
+    AddImmediate(instance_reg, Immediate(instance_size));
     // instance_reg: potential next object start.
-    LoadImmediate(TMP, Immediate(heap->EndAddress(space)), pp);
+    LoadImmediate(TMP, Immediate(heap->EndAddress(space)));
     cmpq(instance_reg, Address(TMP, 0));
     j(ABOVE_EQUAL, failure, near_jump);
     // Successfully allocated the object, now update top to point to
     // next object start and store the class in the class field of object.
-    LoadImmediate(TMP, Immediate(heap->TopAddress(space)), pp);
+    LoadImmediate(TMP, Immediate(heap->TopAddress(space)));
     movq(Address(TMP, 0), instance_reg);
     UpdateAllocationStats(cls.id(), space);
     ASSERT(instance_size >= kHeapObjectTag);
-    AddImmediate(instance_reg, Immediate(kHeapObjectTag - instance_size), pp);
+    AddImmediate(instance_reg, Immediate(kHeapObjectTag - instance_size));
     uword tags = 0;
     tags = RawObject::SizeTag::update(instance_size, tags);
     ASSERT(cls.id() != kIllegalCid);
     tags = RawObject::ClassIdTag::update(cls.id(), tags);
     MoveImmediate(FieldAddress(instance_reg, Object::tags_offset()),
-                  Immediate(tags), pp);
+                  Immediate(tags));
   } else {
     jmp(failure);
   }
 }
 
 
 void Assembler::TryAllocateArray(intptr_t cid,
                                  intptr_t instance_size,
                                  Label* failure,
                                  bool near_jump,
@@ skipping 179 matching lines @@
 void Assembler::LoadClassId(Register result, Register object) {
   ASSERT(RawObject::kClassIdTagPos == kBitsPerInt32);
   ASSERT(RawObject::kClassIdTagSize == kBitsPerInt32);
   ASSERT(sizeof(classid_t) == sizeof(uint32_t));
   const intptr_t class_id_offset = Object::tags_offset() +
       RawObject::kClassIdTagPos / kBitsPerByte;
   movl(result, FieldAddress(object, class_id_offset));
 }
 
 
-void Assembler::LoadClassById(Register result, Register class_id, Register pp) {
+void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(result != class_id);
   LoadIsolate(result);
   const intptr_t offset =
       Isolate::class_table_offset() + ClassTable::table_offset();
   movq(result, Address(result, offset));
   movq(result, Address(result, class_id, TIMES_8, 0));
 }
 
 
-void Assembler::LoadClass(Register result, Register object, Register pp) {
+void Assembler::LoadClass(Register result, Register object) {
   LoadClassId(TMP, object);
-  LoadClassById(result, TMP, pp);
+  LoadClassById(result, TMP);
 }
 
 
 void Assembler::CompareClassId(Register object, intptr_t class_id) {
   LoadClassId(TMP, object);
   cmpl(TMP, Immediate(class_id));
 }
 
 
 void Assembler::SmiUntagOrCheckClass(Register object,
@@ skipping 14 matching lines @@
   movl(TMP, Address(object, TIMES_2, class_id_offset));
   cmpl(TMP, Immediate(class_id));
 }
 
 
 void Assembler::LoadClassIdMayBeSmi(Register result, Register object) {
   ASSERT(result != object);
 
   // Load up a null object. We only need it so we can use LoadClassId on it in
   // the case that object is a Smi.
-  LoadObject(result, Object::null_object(), PP);
+  LoadObject(result, Object::null_object());
   // Check if the object is a Smi.
   testq(object, Immediate(kSmiTagMask));
   // If the object *is* a Smi, use the null object instead.
   cmoveq(object, result);
   // Loads either the cid of the object if it isn't a Smi, or the cid of null
   // if it is a Smi, which will be ignored.
   LoadClassId(result, object);
 
   movq(object, Immediate(kSmiCid));
   // If object is a Smi, move the Smi cid into result. o/w leave alone.
@@ skipping 119 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
   return xmm_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64