Fix breakpad for arm on arm64

client/linux/minidump_writer/linux_ptrace_dumper.cc

 // Copyright (c) 2012, Google Inc.
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 // notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
@@ skipping 188 matching lines @@
   if (sys_ptrace(PTRACE_GETREGSET, tid, (void*)NT_FPREGSET, (void*)&io) == -1) {
     return false;
   }
 #else  // PTRACE_GETREGSET
   void* gp_addr;
   info->GetGeneralPurposeRegisters(&gp_addr, NULL);
   if (sys_ptrace(PTRACE_GETREGS, tid, NULL, gp_addr) == -1) {
     return false;
   }
 
+#if !(defined(__ANDROID__) && defined(__ARM_EABI__))
+  // When running an arm build on an arm64 device, attempting to get the
+  // floating point registers fails. On Android, the floating point registers
+  // aren't written to the cpu context anyway, so just don't get them here.
+  // See http://crbug.com/508324
   void* fp_addr;
   info->GetFloatingPointRegisters(&fp_addr, NULL);
   if (sys_ptrace(PTRACE_GETFPREGS, tid, NULL, fp_addr) == -1) {
     return false;
   }
 #endif
+#endif

[Lei Zhang, 2015/08/04 23:39:34]

nit: add // PTRACE_GETREGSET so it's more obvious whaat the matching #ifdef is.

 
 #if defined(__i386)
 #if !defined(bit_FXSAVE)  // e.g. Clang
 #define bit_FXSAVE bit_FXSR
 #endif
   // Detect if the CPU supports the FXSAVE/FXRSTOR instructions
   int eax, ebx, ecx, edx;
   __cpuid(1, eax, ebx, ecx, edx);
   if (edx & bit_FXSAVE) {
     if (sys_ptrace(PTRACE_GETFPXREGS, tid, NULL, &info->fpxregs) == -1) {
@@ skipping 115 matching lines @@
       }
     }
     dir_reader->PopEntry();
   }
 
   sys_close(fd);
   return true;
 }
 
 }  // namespace google_breakpad