Add the ARM32 FP register table entries, simple arith, and args.

tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll

 ; This tests the NaCl intrinsics not related to atomic operations.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -sandbox \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -sandbox \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1
@@ skipping 132 matching lines @@
   %r = call float @llvm.sqrt.f32(float %x)
   %r2 = call float @llvm.sqrt.f32(float %r)
   %r3 = call float @llvm.sqrt.f32(float -0.0)
   %r4 = fadd float %r2, %r3
   ret float %r4
 }
 ; CHECK-LABEL: test_sqrt_float
 ; CHECK: sqrtss xmm{{.*}}
 ; CHECK: sqrtss xmm{{.*}}
 ; CHECK: sqrtss xmm{{.*}},DWORD PTR
+; ARM32-LABEL: test_sqrt_float
+; ARM32: vsqrt.f32
+; ARM32: vsqrt.f32
+; ARM32: vsqrt.f32
+; ARM32: vadd.f32
 
 define float @test_sqrt_float_mergeable_load(float %x, i32 %iptr) {
 entry:
   %__2 = inttoptr i32 %iptr to float*
   %y = load float, float* %__2, align 4
   %r5 = call float @llvm.sqrt.f32(float %y)
   %r6 = fadd float %x, %r5
   ret float %r6
 }
 ; CHECK-LABEL: test_sqrt_float_mergeable_load
 ; We could fold the load and the sqrt into one operation, but the
 ; current folding only handles load + arithmetic op. The sqrt inst
 ; is considered an intrinsic call and not an arithmetic op.
 ; CHECK: sqrtss xmm{{.*}}
+; ARM32-LABEL: test_sqrt_float_mergeable_load
+; ARM32: vldr s{{.*}}
+; ARM32: vsqrt.f32
 
 define double @test_sqrt_double(double %x, i32 %iptr) {
 entry:
   %r = call double @llvm.sqrt.f64(double %x)
   %r2 = call double @llvm.sqrt.f64(double %r)
   %r3 = call double @llvm.sqrt.f64(double -0.0)
   %r4 = fadd double %r2, %r3
   ret double %r4
 }
 ; CHECK-LABEL: test_sqrt_double
 ; CHECK: sqrtsd xmm{{.*}}
 ; CHECK: sqrtsd xmm{{.*}}
 ; CHECK: sqrtsd xmm{{.*}},QWORD PTR
+; ARM32-LABEL: test_sqrt_double
+; ARM32: vsqrt.f64
+; ARM32: vsqrt.f64
+; ARM32: vsqrt.f64
+; ARM32: vadd.f64
 
 define double @test_sqrt_double_mergeable_load(double %x, i32 %iptr) {
 entry:
   %__2 = inttoptr i32 %iptr to double*
   %y = load double, double* %__2, align 8
   %r5 = call double @llvm.sqrt.f64(double %y)
   %r6 = fadd double %x, %r5
   ret double %r6
 }
 ; CHECK-LABEL: test_sqrt_double_mergeable_load
 ; CHECK: sqrtsd xmm{{.*}}
+; ARM32-LABEL: test_sqrt_double_mergeable_load
+; ARM32: vldr d{{.*}}
+; ARM32: vsqrt.f64
 
 define float @test_sqrt_ignored(float %x, double %y) {
 entry:
   %ignored1 = call float @llvm.sqrt.f32(float %x)
   %ignored2 = call double @llvm.sqrt.f64(double %y)
   ret float 0.0
 }
 ; CHECKO2REM-LABEL: test_sqrt_ignored
 ; CHECKO2REM-NOT: sqrtss
 ; CHECKO2REM-NOT: sqrtsd
@@ skipping 321 matching lines @@
 ; At least 3 copies of esp, but probably more from having to do the allocas.
 ; CHECK: mov {{.*}},esp
 ; CHECK: mov {{.*}},esp
 ; CHECK: mov {{.*}},esp
 ; CHECK: mov esp,{{.*}}
 ; ARM32-LABEL: test_stacksave_multiple
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov sp, {{.*}}