Add the ARM32 FP register table entries, simple arith, and args.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 172 matching lines @@
   // The following are helpers that insert lowered ARM32 instructions
   // with minimal syntactic overhead, so that the lowering code can
   // look as close to assembly as practical.
 
   void _add(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Add::create(Func, Dest, Src0, Src1, Pred));
   }
   void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
-    const bool SetFlags = true;
+    constexpr bool SetFlags = true;
     Context.insert(
         InstARM32Add::create(Func, Dest, Src0, Src1, Pred, SetFlags));
   }
   void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1, Pred));
   }
   void _adjust_stack(int32_t Amount, Operand *SrcAmount) {
     Context.insert(InstARM32AdjustStack::create(
         Func, getPhysicalRegister(RegARM32::Reg_sp), Amount, SrcAmount));
@@ skipping 89 matching lines @@
   void _mvn(Variable *Dest, Operand *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Mvn::create(Func, Dest, Src0, Pred));
   }
   void _orr(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Orr::create(Func, Dest, Src0, Src1, Pred));
   }
   void _orrs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
-    const bool SetFlags = true;
+    constexpr bool SetFlags = true;
     Context.insert(
         InstARM32Orr::create(Func, Dest, Src0, Src1, Pred, SetFlags));
   }
   void _push(const VarList &Sources) {
     Context.insert(InstARM32Push::create(Func, Sources));
   }
   void _pop(const VarList &Dests) {
     Context.insert(InstARM32Pop::create(Func, Dests));
     // Mark dests as modified.
     for (Variable *Dest : Dests)
@@ skipping 13 matching lines @@
   void _rsb(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Rsb::create(Func, Dest, Src0, Src1, Pred));
   }
   void _sbc(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred));
   }
   void _sbcs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
-    const bool SetFlags = true;
+    constexpr bool SetFlags = true;
     Context.insert(
         InstARM32Sbc::create(Func, Dest, Src0, Src1, Pred, SetFlags));
   }
   void _sdiv(Variable *Dest, Variable *Src0, Variable *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Sdiv::create(Func, Dest, Src0, Src1, Pred));
   }
   void _str(Variable *Value, OperandARM32Mem *Addr,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Str::create(Func, Value, Addr, Pred));
   }
   void _sub(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1, Pred));
   }
   void _subs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
-    const bool SetFlags = true;
+    constexpr bool SetFlags = true;
     Context.insert(
         InstARM32Sub::create(Func, Dest, Src0, Src1, Pred, SetFlags));
   }
   void _sxt(Variable *Dest, Variable *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Sxt::create(Func, Dest, Src0, Pred));
   }
   void _tst(Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Tst::create(Func, Src0, Src1, Pred));
   }
   void _trap() { Context.insert(InstARM32Trap::create(Func)); }
   void _udiv(Variable *Dest, Variable *Src0, Variable *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Udiv::create(Func, Dest, Src0, Src1, Pred));
   }
   void _umull(Variable *DestLo, Variable *DestHi, Variable *Src0,
               Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(
         InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1, Pred));
     // Model the modification to the second dest as a fake def.
     // Note that the def is not predicated.
     Context.insert(InstFakeDef::create(Func, DestHi, DestLo));
   }
   void _uxt(Variable *Dest, Variable *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Uxt::create(Func, Dest, Src0, Pred));
   }
+  void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert(InstARM32Vadd::create(Func, Dest, Src0, Src1));
+  }
+  void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert(InstARM32Vdiv::create(Func, Dest, Src0, Src1));
+  }
+  void _vldr(Variable *Dest, OperandARM32Mem *Src,
+             CondARM32::Cond Pred = CondARM32::AL) {
+    Context.insert(InstARM32Vldr::create(Func, Dest, Src, Pred));
+  }
+  // There are a whole bunch of vmov variants, to transfer within
+  // S/D/Q registers, between core integer registers and S/D,
+  // and from small immediates into S/D.
+  // For integer -> S/D/Q there is a variant which takes two integer
+  // register to fill a D, or to fill two consecutive S registers.
+  // Vmov can also be used to insert-element. E.g.,
+  //    "vmov.8 d0[1], r0"
+  // but insert-element is a "two-address" operation where only part of the
+  // register is modified. This cannot model that.
+  //
+  // This represents the simple single source, single dest variants only.
+  void _vmov(Variable *Dest, Operand *Src0) {
+    constexpr CondARM32::Cond Pred = CondARM32::AL;
+    Context.insert(InstARM32Vmov::create(Func, Dest, Src0, Pred));
+  }
+  void _vmul(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert(InstARM32Vmul::create(Func, Dest, Src0, Src1));
+  }
+  void _vsqrt(Variable *Dest, Variable *Src,
+              CondARM32::Cond Pred = CondARM32::AL) {
+    Context.insert(InstARM32Vsqrt::create(Func, Dest, Src, Pred));
+  }
+  void _vsub(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert(InstARM32Vsub::create(Func, Dest, Src0, Src1));
+  }
 
   /// Run a pass through stack variables and ensure that the offsets are legal.
   /// If the offset is not legal, use a new base register that accounts for
   /// the offset, such that the addressing mode offset bits are now legal.
   void legalizeStackSlots();
   /// Returns true if the given Offset can be represented in a stack ldr/str.
   bool isLegalVariableStackOffset(int32_t Offset) const;
   /// Assuming Var needs its offset legalized, define a new base register
   /// centered on the given Var's offset and use it.
   StackVariable *legalizeVariableSlot(Variable *Var, Variable *OrigBaseReg);
@@ skipping 16 matching lines @@
   /// start with registers but extend beyond the available registers can be
   /// split between the registers and the stack. However, this is typically
   /// for passing GPR structs by value, and PNaCl transforms expand this out.
   ///
   /// Also, at the point before the call, the stack must be aligned.
   class CallingConv {
     CallingConv(const CallingConv &) = delete;
     CallingConv &operator=(const CallingConv &) = delete;
 
   public:
-    CallingConv() : NumGPRRegsUsed(0) {}
+    CallingConv() {}
     ~CallingConv() = default;
 
     bool I64InRegs(std::pair<int32_t, int32_t> *Regs);
     bool I32InReg(int32_t *Reg);
+    bool FPInReg(Type Ty, int32_t *Reg);
 
     static constexpr uint32_t ARM32_MAX_GPR_ARG = 4;
+    // Units of S registers still available to S/D/Q arguments.
+    static constexpr uint32_t ARM32_MAX_FP_REG_UNITS = 16;
 
   private:
-    uint32_t NumGPRRegsUsed;
+    uint32_t NumGPRRegsUsed = 0;
+    uint32_t NumFPRegUnits = 0;
   };
 
 private:
   ~TargetARM32() override = default;
 };
 
 class TargetDataARM32 final : public TargetDataLowering {
   TargetDataARM32() = delete;
   TargetDataARM32(const TargetDataARM32 &) = delete;
   TargetDataARM32 &operator=(const TargetDataARM32 &) = delete;
@@ skipping 33 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H