Add the ARM32 FP register table entries, simple arith, and args.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 156 matching lines @@
          TargetInstructionSet::ARM32InstructionSet_Begin) +
         ARM32InstructionSet::Begin);
   }
 }
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), CPUFeatures(Func->getContext()->getFlags()) {
   // TODO: Don't initialize IntegerRegisters and friends every time.
   // Instead, initialize in some sort of static initializer for the
   // class.
+  // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
-  llvm::SmallBitVector FloatRegisters(RegARM32::Reg_NUM);
+  llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
+  llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   ScratchRegs.resize(RegARM32::Reg_NUM);
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
-          isFP)                                                                \
+          isFP32, isFP64, isVec128)                                            \
   IntegerRegisters[RegARM32::val] = isInt;                                     \
-  FloatRegisters[RegARM32::val] = isFP;                                        \
-  VectorRegisters[RegARM32::val] = isFP;                                       \
+  Float32Registers[RegARM32::val] = isFP32;                                    \
+  Float64Registers[RegARM32::val] = isFP64;                                    \
+  VectorRegisters[RegARM32::val] = isVec128;                                   \
   ScratchRegs[RegARM32::val] = scratch;
   REGARM32_TABLE;
 #undef X
   TypeToRegisterSet[IceType_void] = InvalidRegisters;
   TypeToRegisterSet[IceType_i1] = IntegerRegisters;
   TypeToRegisterSet[IceType_i8] = IntegerRegisters;
   TypeToRegisterSet[IceType_i16] = IntegerRegisters;
   TypeToRegisterSet[IceType_i32] = IntegerRegisters;
   TypeToRegisterSet[IceType_i64] = IntegerRegisters;
-  TypeToRegisterSet[IceType_f32] = FloatRegisters;
-  TypeToRegisterSet[IceType_f64] = FloatRegisters;
+  TypeToRegisterSet[IceType_f32] = Float32Registers;
+  TypeToRegisterSet[IceType_f64] = Float64Registers;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
 }
 
 void TargetARM32::translateO2() {
@@ skipping 148 matching lines @@
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
   assert(RegNum < RegARM32::Reg_NUM);
   (void)Ty;
   static const char *RegNames[] = {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
-          isFP)                                                                \
+          isFP32, isFP64, isVec128)                                            \
   name,
       REGARM32_TABLE
 #undef X
   };
 
   return RegNames[RegNum];
 }
 
 Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
   if (Ty == IceType_void)
@@ skipping 51 matching lines @@
   }
   Str << "]";
 }
 
 bool TargetARM32::CallingConv::I64InRegs(std::pair<int32_t, int32_t> *Regs) {
   if (NumGPRRegsUsed >= ARM32_MAX_GPR_ARG)
     return false;
   int32_t RegLo, RegHi;
   // Always start i64 registers at an even register, so this may end
   // up padding away a register.
-  if (NumGPRRegsUsed % 2 != 0) {
-    ++NumGPRRegsUsed;
-  }
+  NumGPRRegsUsed = Utils::applyAlignment(NumGPRRegsUsed, 2);
   RegLo = RegARM32::Reg_r0 + NumGPRRegsUsed;
   ++NumGPRRegsUsed;
   RegHi = RegARM32::Reg_r0 + NumGPRRegsUsed;
   ++NumGPRRegsUsed;
   // If this bumps us past the boundary, don't allocate to a register
   // and leave any previously speculatively consumed registers as consumed.
   if (NumGPRRegsUsed > ARM32_MAX_GPR_ARG)
     return false;
   Regs->first = RegLo;
   Regs->second = RegHi;
   return true;
 }
 
 bool TargetARM32::CallingConv::I32InReg(int32_t *Reg) {
   if (NumGPRRegsUsed >= ARM32_MAX_GPR_ARG)
     return false;
   *Reg = RegARM32::Reg_r0 + NumGPRRegsUsed;
   ++NumGPRRegsUsed;
   return true;
 }
 
+bool TargetARM32::CallingConv::FPInReg(Type Ty, int32_t *Reg) {
+  if (NumFPRegUnits >= ARM32_MAX_FP_REG_UNITS)
+    return false;
+  if (isVectorType(Ty)) {
+    NumFPRegUnits = Utils::applyAlignment(NumFPRegUnits, 4);
+    *Reg = RegARM32::Reg_q0 + (NumFPRegUnits / 4);
+    NumFPRegUnits += 4;
+    // If this bumps us past the boundary, don't allocate to a register
+    // and leave any previously speculatively consumed registers as consumed.
+    if (NumFPRegUnits > ARM32_MAX_FP_REG_UNITS)
+      return false;
+  } else if (Ty == IceType_f64) {
+    NumFPRegUnits = Utils::applyAlignment(NumFPRegUnits, 2);
+    *Reg = RegARM32::Reg_d0 + (NumFPRegUnits / 2);
+    NumFPRegUnits += 2;
+    // If this bumps us past the boundary, don't allocate to a register
+    // and leave any previously speculatively consumed registers as consumed.
+    if (NumFPRegUnits > ARM32_MAX_FP_REG_UNITS)
+      return false;
+  } else {
+    assert(Ty == IceType_f32);
+    *Reg = RegARM32::Reg_s0 + NumFPRegUnits;
+    ++NumFPRegUnits;
+  }
+  return true;
+}
+
 void TargetARM32::lowerArguments() {
   VarList &Args = Func->getArgs();
   TargetARM32::CallingConv CC;
 
   // For each register argument, replace Arg in the argument list with the
   // home register.  Then generate an instruction in the prolog to copy the
   // home register to the assigned location of Arg.
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
   for (SizeT I = 0, E = Args.size(); I < E; ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
-    // TODO(jvoung): handle float/vector types.
-    if (isVectorType(Ty)) {
-      UnimplementedError(Func->getContext()->getFlags());
-      continue;
-    } else if (isFloatingType(Ty)) {
-      UnimplementedError(Func->getContext()->getFlags());
-      continue;
-    } else if (Ty == IceType_i64) {
+    if (Ty == IceType_i64) {
       std::pair<int32_t, int32_t> RegPair;
       if (!CC.I64InRegs(&RegPair))
         continue;
       Variable *RegisterArg = Func->makeVariable(Ty);
       Variable *RegisterLo = Func->makeVariable(IceType_i32);
       Variable *RegisterHi = Func->makeVariable(IceType_i32);
       if (BuildDefs::dump()) {
         RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
         RegisterLo->setName(Func, "home_reg_lo:" + Arg->getName(Func));
         RegisterHi->setName(Func, "home_reg_hi:" + Arg->getName(Func));
       }
       RegisterLo->setRegNum(RegPair.first);
       RegisterLo->setIsArg();
       RegisterHi->setRegNum(RegPair.second);
       RegisterHi->setIsArg();
       RegisterArg->setLoHi(RegisterLo, RegisterHi);
       RegisterArg->setIsArg();
       Arg->setIsArg(false);
 
       Args[I] = RegisterArg;
       Context.insert(InstAssign::create(Func, Arg, RegisterArg));
       continue;
     } else {
-      assert(Ty == IceType_i32);
       int32_t RegNum;
-      if (!CC.I32InReg(&RegNum))
-        continue;
+      if (isVectorType(Ty) || isFloatingType(Ty)) {
+        if (!CC.FPInReg(Ty, &RegNum))
+          continue;
+      } else {
+        assert(Ty == IceType_i32);
+        if (!CC.I32InReg(&RegNum))
+          continue;
+      }
       Variable *RegisterArg = Func->makeVariable(Ty);
       if (BuildDefs::dump()) {
         RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
       }
       RegisterArg->setRegNum(RegNum);
       RegisterArg->setIsArg();
       Arg->setIsArg(false);
 
       Args[I] = RegisterArg;
       Context.insert(InstAssign::create(Func, Arg, RegisterArg));
+      continue;
     }
   }
 }
 
 // Helper function for addProlog().
 //
 // This assumes Arg is an argument passed on the stack.  This sets the
 // frame offset for Arg and updates InArgsSizeBytes according to Arg's
 // width.  For an I64 arg that has been split into Lo and Hi components,
 // it calls itself recursively on the components, taking care to handle
@@ skipping 17 matching lines @@
   Arg->setStackOffset(BasicFrameOffset + InArgsSizeBytes);
   InArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   // If the argument variable has been assigned a register, we need to load
   // the value from the stack slot.
   if (Arg->hasReg()) {
     assert(Ty != IceType_i64);
     OperandARM32Mem *Mem = OperandARM32Mem::create(
         Func, Ty, FramePtr, llvm::cast<ConstantInteger32>(
                                 Ctx->getConstantInt32(Arg->getStackOffset())));
     if (isVectorType(Arg->getType())) {
+      // Use vld1.$elem or something?
       UnimplementedError(Func->getContext()->getFlags());
+    } else if (isFloatingType(Arg->getType())) {
+      _vldr(Arg, Mem);
     } else {
       _ldr(Arg, Mem);
     }
     // This argument-copying instruction uses an explicit
     // OperandARM32Mem operand instead of a Variable, so its
     // fill-from-stack operation has to be tracked separately for
     // statistics.
     Ctx->statsUpdateFills();
   }
 }
@@ skipping 150 matching lines @@
   if (!UsesFramePointer)
     BasicFrameOffset += SpillAreaSizeBytes;
 
   const VarList &Args = Func->getArgs();
   size_t InArgsSizeBytes = 0;
   TargetARM32::CallingConv CC;
   for (Variable *Arg : Args) {
     Type Ty = Arg->getType();
     bool InRegs = false;
     // Skip arguments passed in registers.
-    if (isVectorType(Ty)) {
-      UnimplementedError(Func->getContext()->getFlags());
-      continue;
-    } else if (isFloatingType(Ty)) {
-      UnimplementedError(Func->getContext()->getFlags());
-      continue;
+    if (isVectorType(Ty) || isFloatingType(Ty)) {
+      int32_t DummyReg;
+      InRegs = CC.FPInReg(Ty, &DummyReg);
     } else if (Ty == IceType_i64) {
       std::pair<int32_t, int32_t> DummyRegs;
       InRegs = CC.I64InRegs(&DummyRegs);
     } else {
       assert(Ty == IceType_i32);
       int32_t DummyReg;
       InRegs = CC.I32InReg(&DummyReg);
     }
     if (!InRegs)
       finishArgumentLowering(Arg, FramePtr, BasicFrameOffset, InArgsSizeBytes);
@@ skipping 107 matching lines @@
     RetValue = llvm::cast<Variable>(RI->getSrc(0));
   _bundle_lock();
   _bic(LR, LR, RetMask);
   _ret(LR, RetValue);
   _bundle_unlock();
   RI->setDeleted();
 }
 
 bool TargetARM32::isLegalVariableStackOffset(int32_t Offset) const {
   constexpr bool SignExt = false;
+  // TODO(jvoung): vldr of FP stack slots has a different limit from the
+  // plain stackSlotType().
   return OperandARM32Mem::canHoldOffset(stackSlotType(), SignExt, Offset);
 }
 
 StackVariable *TargetARM32::legalizeVariableSlot(Variable *Var,
                                                  Variable *OrigBaseReg) {
   int32_t Offset = Var->getStackOffset();
   // Legalize will likely need a movw/movt combination, but if the top
   // bits are all 0 from negating the offset and subtracting, we could
   // use that instead.
   bool ShouldSub = (-Offset & 0xFFFF0000) == 0;
@@ skipping 243 matching lines @@
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
-          isFP)                                                                \
+          isFP32, isFP64, isVec128)                                            \
   if (scratch && (Include & RegSet_CallerSave))                                \
     Registers[RegARM32::val] = true;                                           \
   if (preserved && (Include & RegSet_CalleeSave))                              \
     Registers[RegARM32::val] = true;                                           \
   if (stackptr && (Include & RegSet_StackPointer))                             \
     Registers[RegARM32::val] = true;                                           \
   if (frameptr && (Include & RegSet_FramePointer))                             \
     Registers[RegARM32::val] = true;                                           \
   if (scratch && (Exclude & RegSet_CallerSave))                                \
     Registers[RegARM32::val] = false;                                          \
@@ skipping 376 matching lines @@
     case InstArithmetic::Sdiv:
     case InstArithmetic::Urem:
     case InstArithmetic::Srem:
       llvm_unreachable("Call-helper-involved instruction for i64 type "
                        "should have already been handled before");
       return;
     }
     return;
   } else if (isVectorType(Dest->getType())) {
     UnimplementedError(Func->getContext()->getFlags());
+    // Add a fake def to keep liveness consistent in the meantime.
+    Context.insert(InstFakeDef::create(Func, Dest));
     return;
   }
   // Dest->getType() is a non-i64 scalar.
   Variable *Src0R = legalizeToReg(Src0);
   Variable *T = makeReg(Dest->getType());
   // Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
   // difficult to determine (constant may be moved to a register).
   switch (Inst->getOp()) {
   default:
@@ skipping 15 matching lines @@
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_uxt, &TargetARM32::_udiv,
                  H_urem_i32, IsRemainder);
     return;
   }
   case InstArithmetic::Srem: {
     constexpr bool IsRemainder = true;
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_sxt, &TargetARM32::_sdiv,
                  H_srem_i32, IsRemainder);
     return;
   }
+  case InstArithmetic::Frem: {
+    const SizeT MaxSrcs = 2;
+    Type Ty = Dest->getType();
+    InstCall *Call = makeHelperCall(
+        isFloat32Asserting32Or64(Ty) ? H_frem_f32 : H_frem_f64, Dest, MaxSrcs);
+    Call->addArg(Src0R);
+    Call->addArg(Src1);
+    lowerCall(Call);
+    return;
+  }
+  }
+
+  // Handle floating point arithmetic separately: they require Src1 to be
+  // legalized to a register.
+  switch (Inst->getOp()) {
+  default:
+    break;
+  case InstArithmetic::Fadd: {
+    Variable *Src1R = legalizeToReg(Src1);
+    _vadd(T, Src0R, Src1R);
+    _vmov(Dest, T);
+    return;
+  }
+  case InstArithmetic::Fsub: {
+    Variable *Src1R = legalizeToReg(Src1);
+    _vsub(T, Src0R, Src1R);
+    _vmov(Dest, T);
+    return;
+  }
+  case InstArithmetic::Fmul: {
+    Variable *Src1R = legalizeToReg(Src1);
+    _vmul(T, Src0R, Src1R);
+    _vmov(Dest, T);
+    return;
+  }
+  case InstArithmetic::Fdiv: {
+    Variable *Src1R = legalizeToReg(Src1);
+    _vdiv(T, Src0R, Src1R);
+    _vmov(Dest, T);
+    return;
+  }
   }
 
   Operand *Src1RF = legalize(Src1, Legal_Reg | Legal_Flex);
   switch (Inst->getOp()) {
   case InstArithmetic::_num:
     llvm_unreachable("Unknown arithmetic operator");
     return;
   case InstArithmetic::Add:
     _add(T, Src0R, Src1RF);
     _mov(Dest, T);
@@ skipping 32 matching lines @@
     _asr(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Udiv:
   case InstArithmetic::Sdiv:
   case InstArithmetic::Urem:
   case InstArithmetic::Srem:
     llvm_unreachable("Integer div/rem should have been handled earlier.");
     return;
   case InstArithmetic::Fadd:
-    UnimplementedError(Func->getContext()->getFlags());
-    return;
   case InstArithmetic::Fsub:
-    UnimplementedError(Func->getContext()->getFlags());
-    return;
   case InstArithmetic::Fmul:
-    UnimplementedError(Func->getContext()->getFlags());
-    return;
   case InstArithmetic::Fdiv:
-    UnimplementedError(Func->getContext()->getFlags());
-    return;
   case InstArithmetic::Frem:
-    UnimplementedError(Func->getContext()->getFlags());
+    llvm_unreachable("Floating point arith should have been handled earlier.");
     return;
   }
 }
 
 void TargetARM32::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
@@ skipping 14 matching lines @@
       // helps allow the use of Flex operands.
       NewSrc = legalize(Src0, Legal_Reg | Legal_Flex, Dest->getRegNum());
     } else {
       // Dest could be a stack operand. Since we could potentially need
       // to do a Store (and store can only have Register operands),
       // legalize this to a register.
       NewSrc = legalize(Src0, Legal_Reg);
     }
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
+    } else if (isFloatingType(Dest->getType())) {
+      Variable *SrcR = legalizeToReg(NewSrc);
+      _vmov(Dest, SrcR);
     } else {
       _mov(Dest, NewSrc);
     }
   }
 }
 
 void TargetARM32::lowerBr(const InstBr *Inst) {
   if (Inst->isUnconditional()) {
     _br(Inst->getTargetUnconditional());
     return;
   }
   Operand *Cond = Inst->getCondition();
   // TODO(jvoung): Handle folding opportunities.
 
   Variable *Src0R = legalizeToReg(Cond);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0R, Zero);
   _br(Inst->getTargetTrue(), Inst->getTargetFalse(), CondARM32::NE);
 }
 
 void TargetARM32::lowerCall(const InstCall *Instr) {
   MaybeLeafFunc = false;
   NeedsStackAlignment = true;
 
   // Assign arguments to registers and stack. Also reserve stack.
   TargetARM32::CallingConv CC;
   // Pair of Arg Operand -> GPR number assignments.
   llvm::SmallVector<std::pair<Operand *, int32_t>,
                     TargetARM32::CallingConv::ARM32_MAX_GPR_ARG> GPRArgs;
+  llvm::SmallVector<std::pair<Operand *, int32_t>,
+                    TargetARM32::CallingConv::ARM32_MAX_FP_REG_UNITS> FPArgs;
   // Pair of Arg Operand -> stack offset.
   llvm::SmallVector<std::pair<Operand *, int32_t>, 8> StackArgs;
   int32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = legalizeUndef(Instr->getArg(i));
     Type Ty = Arg->getType();
     bool InRegs = false;
-    if (isVectorType(Ty)) {
-      UnimplementedError(Func->getContext()->getFlags());
-    } else if (isFloatingType(Ty)) {
-      UnimplementedError(Func->getContext()->getFlags());
-    } else if (Ty == IceType_i64) {
+    if (Ty == IceType_i64) {
       std::pair<int32_t, int32_t> Regs;
       if (CC.I64InRegs(&Regs)) {
         InRegs = true;
         Operand *Lo = loOperand(Arg);
         Operand *Hi = hiOperand(Arg);
         GPRArgs.push_back(std::make_pair(Lo, Regs.first));
         GPRArgs.push_back(std::make_pair(Hi, Regs.second));
       }
+    } else if (isVectorType(Ty) || isFloatingType(Ty)) {
+      int32_t Reg;
+      if (CC.FPInReg(Ty, &Reg)) {
+        InRegs = true;
+        FPArgs.push_back(std::make_pair(Arg, Reg));
+      }
     } else {
       assert(Ty == IceType_i32);
       int32_t Reg;
       if (CC.I32InReg(&Reg)) {
         InRegs = true;
         GPRArgs.push_back(std::make_pair(Arg, Reg));
       }
     }
 
     if (!InRegs) {
@@ skipping 42 matching lines @@
   }
 
   // Copy arguments to be passed in registers to the appropriate registers.
   for (auto &GPRArg : GPRArgs) {
     Variable *Reg = legalizeToReg(GPRArg.first, GPRArg.second);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
     Context.insert(InstFakeUse::create(Func, Reg));
   }
+  for (auto &FPArg : FPArgs) {
+    Variable *Reg = legalizeToReg(FPArg.first, FPArg.second);
+    Context.insert(InstFakeUse::create(Func, Reg));
+  }
 
   // Generate the call instruction.  Assign its result to a temporary
   // with high register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
   Variable *ReturnRegHi = nullptr;
   if (Dest) {
     switch (Dest->getType()) {
     case IceType_NUM:
       llvm_unreachable("Invalid Call dest type");
       break;
     case IceType_void:
       break;
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
     case IceType_i32:
       ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_r0);
       break;
     case IceType_i64:
       ReturnReg = makeReg(IceType_i32, RegARM32::Reg_r0);
       ReturnRegHi = makeReg(IceType_i32, RegARM32::Reg_r1);
       break;
     case IceType_f32:
+      ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_s0);
+      break;
     case IceType_f64:
-      // Use S and D regs.
-      UnimplementedError(Func->getContext()->getFlags());
+      ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_d0);
       break;
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
-      // Use Q regs.
-      UnimplementedError(Func->getContext()->getFlags());
+      ReturnReg = makeReg(Dest->getType(), RegARM32::Reg_q0);
       break;
     }
   }
   Operand *CallTarget = Instr->getCallTarget();
   // TODO(jvoung): Handle sandboxing.
   // const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
 
   // Allow ConstantRelocatable to be left alone as a direct call,
   // but force other constants like ConstantInteger32 to be in
   // a register and make it an indirect call.
@@ skipping 29 matching lines @@
   // Assign the result of the call to Dest.
   if (ReturnReg) {
     if (ReturnRegHi) {
       assert(Dest->getType() == IceType_i64);
       split64(Dest);
       Variable *DestLo = Dest->getLo();
       Variable *DestHi = Dest->getHi();
       _mov(DestLo, ReturnReg);
       _mov(DestHi, ReturnRegHi);
     } else {
-      assert(Dest->getType() == IceType_i32 || Dest->getType() == IceType_i16 ||
-             Dest->getType() == IceType_i8 || Dest->getType() == IceType_i1 ||
-             isVectorType(Dest->getType()));
       if (isFloatingType(Dest->getType()) || isVectorType(Dest->getType())) {
-        UnimplementedError(Func->getContext()->getFlags());
+        _vmov(Dest, ReturnReg);
       } else {
+        assert(isIntegerType(Dest->getType()) &&
+               typeWidthInBytes(Dest->getType()) <= 4);
         _mov(Dest, ReturnReg);
       }
     }
   }
 }
 
 void TargetARM32::lowerCast(const InstCast *Inst) {
   InstCast::OpKind CastKind = Inst->getCastKind();
   Variable *Dest = Inst->getDest();
   Operand *Src0 = legalizeUndef(Inst->getSrc(0));
@@ skipping 412 matching lines @@
     } else {
       ValLoR = legalizeToReg(Val);
       Variable *T = makeReg(IceType_i32);
       _rbit(T, ValLoR);
       ValLoR = T;
     }
     lowerCLZ(Instr->getDest(), ValLoR, ValHiR);
     return;
   }
   case Intrinsics::Fabs: {
+    // Add a fake def to keep liveness consistent in the meantime.
+    Context.insert(InstFakeDef::create(Func, Instr->getDest()));
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   case Intrinsics::Longjmp: {
     InstCall *Call = makeHelperCall(H_call_longjmp, nullptr, 2);
     Call->addArg(Instr->getArg(0));
     Call->addArg(Instr->getArg(1));
     lowerCall(Call);
     return;
   }
@@ skipping 41 matching lines @@
     }
     return;
   }
   case Intrinsics::Setjmp: {
     InstCall *Call = makeHelperCall(H_call_setjmp, Instr->getDest(), 1);
     Call->addArg(Instr->getArg(0));
     lowerCall(Call);
     return;
   }
   case Intrinsics::Sqrt: {
-    UnimplementedError(Func->getContext()->getFlags());
+    Variable *Src = legalizeToReg(Instr->getArg(0));
+    Variable *Dest = Instr->getDest();
+    Variable *T = makeReg(Dest->getType());
+    _vsqrt(T, Src);
+    _vmov(Dest, T);
     return;
   }
   case Intrinsics::Stacksave: {
     Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
     Variable *Dest = Instr->getDest();
     _mov(Dest, SP);
     return;
   }
   case Intrinsics::Stackrestore: {
     Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
@@ skipping 67 matching lines @@
 }
 
 void TargetARM32::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetARM32::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = Inst->getRetValue();
-    if (Src0->getType() == IceType_i64) {
+    Type Ty = Src0->getType();
+    if (Ty == IceType_i64) {
       Src0 = legalizeUndef(Src0);
       Variable *R0 = legalizeToReg(loOperand(Src0), RegARM32::Reg_r0);
       Variable *R1 = legalizeToReg(hiOperand(Src0), RegARM32::Reg_r1);
       Reg = R0;
       Context.insert(InstFakeUse::create(Func, R1));
-    } else if (isScalarFloatingType(Src0->getType())) {
-      UnimplementedError(Func->getContext()->getFlags());
+    } else if (Ty == IceType_f32) {
+      Variable *S0 = legalizeToReg(Src0, RegARM32::Reg_s0);
+      Reg = S0;
+    } else if (Ty == IceType_f64) {
+      Variable *D0 = legalizeToReg(Src0, RegARM32::Reg_d0);
+      Reg = D0;
     } else if (isVectorType(Src0->getType())) {
-      UnimplementedError(Func->getContext()->getFlags());
+      Variable *Q0 = legalizeToReg(Src0, RegARM32::Reg_q0);
+      Reg = Q0;
     } else {
       Operand *Src0F = legalize(Src0, Legal_Reg | Legal_Flex);
       _mov(Reg, Src0F, CondARM32::AL, RegARM32::Reg_r0);
     }
   }
   // Add a ret instruction even if sandboxing is enabled, because
   // addEpilog explicitly looks for a ret instruction as a marker for
   // where to insert the frame removal instructions.
   // addEpilog is responsible for restoring the "lr" register as needed
   // prior to this ret instruction.
@@ skipping 126 matching lines @@
   Variable *Reg = makeReg(Ty, RegNum);
   UnimplementedError(Func->getContext()->getFlags());
   return Reg;
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
 Variable *TargetARM32::copyToReg(Operand *Src, int32_t RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
-  if (isVectorType(Ty)) {
-    UnimplementedError(Func->getContext()->getFlags());
+  if (isVectorType(Ty) || isFloatingType(Ty)) {
+    _vmov(Reg, Src);
   } else {
     // Mov's Src operand can really only be the flexible second operand type
     // or a register. Users should guarantee that.
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
                                int32_t RegNum) {
@@ skipping 28 matching lines @@
         Mem = OperandARM32Mem::create(Func, Ty, RegBase, RegIndex,
                                       Mem->getShiftOp(), Mem->getShiftAmt(),
                                       Mem->getAddrMode());
       } else {
         Mem = OperandARM32Mem::create(Func, Ty, RegBase, Mem->getOffset(),
                                       Mem->getAddrMode());
       }
     }
     if (!(Allowed & Legal_Mem)) {
       Variable *Reg = makeReg(Ty, RegNum);
-      _ldr(Reg, Mem);
+      if (isVectorType(Ty)) {
+        UnimplementedError(Func->getContext()->getFlags());
+      } else if (isFloatingType(Ty)) {
+        _vldr(Reg, Mem);
+      } else {
+        _ldr(Reg, Mem);
+      }
       From = Reg;
     } else {
       From = Mem;
     }
     return From;
   }
 
   if (auto Flex = llvm::dyn_cast<OperandARM32Flex>(From)) {
     if (!(Allowed & Legal_Flex)) {
       if (auto FlexReg = llvm::dyn_cast<OperandARM32FlexReg>(Flex)) {
@@ skipping 49 matching lines @@
           _movt(Reg, Ctx->getConstantInt32(UpperBits));
         }
         return Reg;
       }
     } else if (auto *C = llvm::dyn_cast<ConstantRelocatable>(From)) {
       Variable *Reg = makeReg(Ty, RegNum);
       _movw(Reg, C);
       _movt(Reg, C);
       return Reg;
     } else {
+      assert(isScalarFloatingType(Ty));
       // Load floats/doubles from literal pool.
-      UnimplementedError(Func->getContext()->getFlags());
-      From = copyToReg(From, RegNum);
+      // TODO(jvoung): Allow certain immediates to be encoded directly in
+      // an operand. See Table A7-18 of the ARM manual:
+      // "Floating-point modified immediate constants".
+      // Or, for 32-bit floating point numbers, just encode the raw bits
+      // into a movw/movt pair to GPR, and vmov to an SREG, instead of using
+      // a movw/movt pair to get the const-pool address then loading to SREG.
+      std::string Buffer;
+      llvm::raw_string_ostream StrBuf(Buffer);
+      llvm::cast<Constant>(From)->emitPoolLabel(StrBuf);
+      llvm::cast<Constant>(From)->setShouldBePooled(true);
+      Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
+      Variable *BaseReg = makeReg(getPointerType());
+      _movw(BaseReg, Offset);
+      _movt(BaseReg, Offset);
+      From = formMemoryOperand(BaseReg, Ty);
+      return copyToReg(From, RegNum);
     }
-    return From;
   }
 
   if (auto Var = llvm::dyn_cast<Variable>(From)) {
     // Check if the variable is guaranteed a physical register.  This
     // can happen either when the variable is pre-colored or when it is
     // assigned infinite weight.
     bool MustHaveRegister = (Var->hasReg() || Var->getWeight().isInf());
     // We need a new physical register for the operand if:
     //   Mem is not allowed and Var isn't guaranteed a physical
     //   register, or
@@ skipping 197 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice