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Issue 1266263003: Add the ARM32 FP register table entries, simple arith, and args. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: format more Created 5 years, 4 months ago
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1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of ARM32 instructions in the form of x-macros. 10 // This file defines properties of ARM32 instructions in the form of x-macros.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF 14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF
15 #define SUBZERO_SRC_ICEINSTARM32_DEF 15 #define SUBZERO_SRC_ICEINSTARM32_DEF
16 16
17 // NOTE: PC and SP are not considered isInt, to avoid register allocating. 17 // NOTE: PC and SP are not considered isInt, to avoid register allocating.
18 // 18 //
19 // For the NaCl sandbox we also need to r9 for TLS, so just reserve always. 19 // For the NaCl sandbox we also need to r9 for TLS, so just reserve always.
20 // TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off 20 // TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off
21 // (native mode). 21 // (native mode).
22 // 22 //
23 // IP is not considered isInt to reserve it as a scratch register. A scratch 23 // IP is not considered isInt to reserve it as a scratch register. A scratch
24 // register is useful for expanding instructions post-register allocation. 24 // register is useful for expanding instructions post-register allocation.
25 // 25 //
26 // LR is not considered isInt to avoid being allocated as a register. 26 // LR is not considered isInt to avoid being allocated as a register.
27 // It is technically preserved, but save/restore is handled separately, 27 // It is technically preserved, but save/restore is handled separately,
28 // based on whether or not the function MaybeLeafFunc. 28 // based on whether or not the function MaybeLeafFunc.
29 #define REGARM32_GPR_TABLE \ 29 #define REGARM32_GPR_TABLE \
30 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \ 30 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
31 X(Reg_r0, = 0, "r0", 1, 0, 0, 0, 1, 0) \ 31 isInt, isFP32, isFP64, isVec128 */ \
32 X(Reg_r1, = Reg_r0 + 1, "r1", 1, 0, 0, 0, 1, 0) \ 32 X(Reg_r0, 0, "r0", 1, 0, 0, 0, 1, 0, 0, 0) \
33 X(Reg_r2, = Reg_r0 + 2, "r2", 1, 0, 0, 0, 1, 0) \ 33 X(Reg_r1, 1, "r1", 1, 0, 0, 0, 1, 0, 0, 0) \
34 X(Reg_r3, = Reg_r0 + 3, "r3", 1, 0, 0, 0, 1, 0) \ 34 X(Reg_r2, 2, "r2", 1, 0, 0, 0, 1, 0, 0, 0) \
35 X(Reg_r4, = Reg_r0 + 4, "r4", 0, 1, 0, 0, 1, 0) \ 35 X(Reg_r3, 3, "r3", 1, 0, 0, 0, 1, 0, 0, 0) \
36 X(Reg_r5, = Reg_r0 + 5, "r5", 0, 1, 0, 0, 1, 0) \ 36 X(Reg_r4, 4, "r4", 0, 1, 0, 0, 1, 0, 0, 0) \
37 X(Reg_r6, = Reg_r0 + 6, "r6", 0, 1, 0, 0, 1, 0) \ 37 X(Reg_r5, 5, "r5", 0, 1, 0, 0, 1, 0, 0, 0) \
38 X(Reg_r7, = Reg_r0 + 7, "r7", 0, 1, 0, 0, 1, 0) \ 38 X(Reg_r6, 6, "r6", 0, 1, 0, 0, 1, 0, 0, 0) \
39 X(Reg_r8, = Reg_r0 + 8, "r8", 0, 1, 0, 0, 1, 0) \ 39 X(Reg_r7, 7, "r7", 0, 1, 0, 0, 1, 0, 0, 0) \
40 X(Reg_r9, = Reg_r0 + 9, "r9", 0, 1, 0, 0, 0, 0) \ 40 X(Reg_r8, 8, "r8", 0, 1, 0, 0, 1, 0, 0, 0) \
41 X(Reg_r10, = Reg_r0 + 10, "r10", 0, 1, 0, 0, 1, 0) \ 41 X(Reg_r9, 9, "r9", 0, 1, 0, 0, 0, 0, 0, 0) \
42 X(Reg_fp, = Reg_r0 + 11, "fp", 0, 1, 0, 1, 1, 0) \ 42 X(Reg_r10, 10, "r10", 0, 1, 0, 0, 1, 0, 0, 0) \
43 X(Reg_ip, = Reg_r0 + 12, "ip", 1, 0, 0, 0, 0, 0) \ 43 X(Reg_fp, 11, "fp", 0, 1, 0, 1, 1, 0, 0, 0) \
44 X(Reg_sp, = Reg_r0 + 13, "sp", 0, 0, 1, 0, 0, 0) \ 44 X(Reg_ip, 12, "ip", 1, 0, 0, 0, 0, 0, 0, 0) \
45 X(Reg_lr, = Reg_r0 + 14, "lr", 0, 0, 0, 0, 0, 0) \ 45 X(Reg_sp, 13, "sp", 0, 0, 1, 0, 0, 0, 0, 0) \
46 X(Reg_pc, = Reg_r0 + 15, "pc", 0, 0, 0, 0, 0, 0) \ 46 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0) \
47 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 47 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0)
48 // isInt, isFP) 48 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
49 49 // isInt, isFP32, isFP64, isVec128)
50 // TODO(jvoung): List FP registers and know S0 == D0 == Q0, etc. 50
51 // Be able to grab even registers, and the corresponding odd register 51 // TODO(jvoung): Be able to grab even registers, and the corresponding odd
52 // for each even register. 52 // register for each even register. Want "register units" to encapsulate
53 // the aliasing/overlap.
54 //
55 // S registers 0-15 are scratch, but 16-31 are preserved.
56 // Regenerate this with the following python script:
57 //
58 // def print_sregs():
59 // for i in xrange(0, 32):
60 // is_scratch = 1 if i < 16 else 0
61 // is_preserved = 1 if i >= 16 else 0
62 // print ('X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
63 // '{scratch}, {preserved}, 0, 0, 0, 1, 0, 0) \\').format(
64 // regnum=i, scratch=is_scratch, preserved=is_preserved)
65 //
66 // print_sregs()
67 //
68 #define REGARM32_FP32_TABLE \
69 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
70 isInt, isFP32, isFP64, isVec128 */ \
71 X(Reg_s0, 0, "s0", 1, 0, 0, 0, 0, 1, 0, 0) \
72 X(Reg_s1, 1, "s1", 1, 0, 0, 0, 0, 1, 0, 0) \
73 X(Reg_s2, 2, "s2", 1, 0, 0, 0, 0, 1, 0, 0) \
74 X(Reg_s3, 3, "s3", 1, 0, 0, 0, 0, 1, 0, 0) \
75 X(Reg_s4, 4, "s4", 1, 0, 0, 0, 0, 1, 0, 0) \
76 X(Reg_s5, 5, "s5", 1, 0, 0, 0, 0, 1, 0, 0) \
77 X(Reg_s6, 6, "s6", 1, 0, 0, 0, 0, 1, 0, 0) \
78 X(Reg_s7, 7, "s7", 1, 0, 0, 0, 0, 1, 0, 0) \
79 X(Reg_s8, 8, "s8", 1, 0, 0, 0, 0, 1, 0, 0) \
80 X(Reg_s9, 9, "s9", 1, 0, 0, 0, 0, 1, 0, 0) \
81 X(Reg_s10, 10, "s10", 1, 0, 0, 0, 0, 1, 0, 0) \
82 X(Reg_s11, 11, "s11", 1, 0, 0, 0, 0, 1, 0, 0) \
83 X(Reg_s12, 12, "s12", 1, 0, 0, 0, 0, 1, 0, 0) \
84 X(Reg_s13, 13, "s13", 1, 0, 0, 0, 0, 1, 0, 0) \
85 X(Reg_s14, 14, "s14", 1, 0, 0, 0, 0, 1, 0, 0) \
86 X(Reg_s15, 15, "s15", 1, 0, 0, 0, 0, 1, 0, 0) \
87 X(Reg_s16, 16, "s16", 0, 1, 0, 0, 0, 1, 0, 0) \
88 X(Reg_s17, 17, "s17", 0, 1, 0, 0, 0, 1, 0, 0) \
89 X(Reg_s18, 18, "s18", 0, 1, 0, 0, 0, 1, 0, 0) \
90 X(Reg_s19, 19, "s19", 0, 1, 0, 0, 0, 1, 0, 0) \
91 X(Reg_s20, 20, "s20", 0, 1, 0, 0, 0, 1, 0, 0) \
92 X(Reg_s21, 21, "s21", 0, 1, 0, 0, 0, 1, 0, 0) \
93 X(Reg_s22, 22, "s22", 0, 1, 0, 0, 0, 1, 0, 0) \
94 X(Reg_s23, 23, "s23", 0, 1, 0, 0, 0, 1, 0, 0) \
95 X(Reg_s24, 24, "s24", 0, 1, 0, 0, 0, 1, 0, 0) \
96 X(Reg_s25, 25, "s25", 0, 1, 0, 0, 0, 1, 0, 0) \
97 X(Reg_s26, 26, "s26", 0, 1, 0, 0, 0, 1, 0, 0) \
98 X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 1, 0, 0) \
99 X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 1, 0, 0) \
100 X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 1, 0, 0) \
101 X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 1, 0, 0) \
102 X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 1, 0, 0)
103 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
104 // isInt, isFP32, isFP64, isVec128)
105
106 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31
107 // are also scratch (if supported by the D32 feature vs D16).
108 //
109 // Regenerate this with the following python script:
110 // def print_dregs():
111 // for i in xrange(0, 32):
112 // is_scratch = 1 if (i < 8 or i >= 16) else 0
113 // is_preserved = 1 if (8 <= i and i < 16) else 0
114 // print ('X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
115 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0) \\').format(
116 // regnum=i, scratch=is_scratch, preserved=is_preserved)
117 //
118 // print_dregs()
119 //
120 #define REGARM32_FP64_TABLE \
121 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
122 isInt, isFP32, isFP64, isVec128 */ \
123 X(Reg_d0, 0, "d0", 1, 0, 0, 0, 0, 0, 1, 0) \
124 X(Reg_d1, 1, "d1", 1, 0, 0, 0, 0, 0, 1, 0) \
125 X(Reg_d2, 2, "d2", 1, 0, 0, 0, 0, 0, 1, 0) \
126 X(Reg_d3, 3, "d3", 1, 0, 0, 0, 0, 0, 1, 0) \
127 X(Reg_d4, 4, "d4", 1, 0, 0, 0, 0, 0, 1, 0) \
128 X(Reg_d5, 5, "d5", 1, 0, 0, 0, 0, 0, 1, 0) \
129 X(Reg_d6, 6, "d6", 1, 0, 0, 0, 0, 0, 1, 0) \
130 X(Reg_d7, 7, "d7", 1, 0, 0, 0, 0, 0, 1, 0) \
131 X(Reg_d8, 8, "d8", 0, 1, 0, 0, 0, 0, 1, 0) \
132 X(Reg_d9, 9, "d9", 0, 1, 0, 0, 0, 0, 1, 0) \
133 X(Reg_d10, 10, "d10", 0, 1, 0, 0, 0, 0, 1, 0) \
134 X(Reg_d11, 11, "d11", 0, 1, 0, 0, 0, 0, 1, 0) \
135 X(Reg_d12, 12, "d12", 0, 1, 0, 0, 0, 0, 1, 0) \
136 X(Reg_d13, 13, "d13", 0, 1, 0, 0, 0, 0, 1, 0) \
137 X(Reg_d14, 14, "d14", 0, 1, 0, 0, 0, 0, 1, 0) \
138 X(Reg_d15, 15, "d15", 0, 1, 0, 0, 0, 0, 1, 0) \
139 X(Reg_d16, 16, "d16", 1, 0, 0, 0, 0, 0, 1, 0) \
140 X(Reg_d17, 17, "d17", 1, 0, 0, 0, 0, 0, 1, 0) \
141 X(Reg_d18, 18, "d18", 1, 0, 0, 0, 0, 0, 1, 0) \
142 X(Reg_d19, 19, "d19", 1, 0, 0, 0, 0, 0, 1, 0) \
143 X(Reg_d20, 20, "d20", 1, 0, 0, 0, 0, 0, 1, 0) \
144 X(Reg_d21, 21, "d21", 1, 0, 0, 0, 0, 0, 1, 0) \
145 X(Reg_d22, 22, "d22", 1, 0, 0, 0, 0, 0, 1, 0) \
146 X(Reg_d23, 23, "d23", 1, 0, 0, 0, 0, 0, 1, 0) \
147 X(Reg_d24, 24, "d24", 1, 0, 0, 0, 0, 0, 1, 0) \
148 X(Reg_d25, 25, "d25", 1, 0, 0, 0, 0, 0, 1, 0) \
149 X(Reg_d26, 26, "d26", 1, 0, 0, 0, 0, 0, 1, 0) \
150 X(Reg_d27, 27, "d27", 1, 0, 0, 0, 0, 0, 1, 0) \
151 X(Reg_d28, 28, "d28", 1, 0, 0, 0, 0, 0, 1, 0) \
152 X(Reg_d29, 29, "d29", 1, 0, 0, 0, 0, 0, 1, 0) \
153 X(Reg_d30, 30, "d30", 1, 0, 0, 0, 0, 0, 1, 0) \
154 X(Reg_d31, 31, "d31", 1, 0, 0, 0, 0, 0, 1, 0)
155 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
156 // isInt, isFP32, isFP64, isVec128)
157
158 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15
159 // are also scratch (if supported by the D32 feature).
160 //
161 // Regenerate this with the following python script:
162 // def print_qregs():
163 // for i in xrange(0, 16):
164 // is_scratch = 1 if (i < 4 or i >= 8) else 0
165 // is_preserved = 1 if (4 <= i and i < 8) else 0
166 // print ('X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
167 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1) \\').format(
168 // regnum=i, scratch=is_scratch, preserved=is_preserved)
169 //
170 // print_qregs()
171 //
172 #define REGARM32_VEC128_TABLE \
173 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
174 isInt, isFP32, isFP64, isVec128 */ \
175 X(Reg_q0, 0, "q0", 1, 0, 0, 0, 0, 0, 0, 1) \
176 X(Reg_q1, 1, "q1", 1, 0, 0, 0, 0, 0, 0, 1) \
177 X(Reg_q2, 2, "q2", 1, 0, 0, 0, 0, 0, 0, 1) \
178 X(Reg_q3, 3, "q3", 1, 0, 0, 0, 0, 0, 0, 1) \
179 X(Reg_q4, 4, "q4", 0, 1, 0, 0, 0, 0, 0, 1) \
180 X(Reg_q5, 5, "q5", 0, 1, 0, 0, 0, 0, 0, 1) \
181 X(Reg_q6, 6, "q6", 0, 1, 0, 0, 0, 0, 0, 1) \
182 X(Reg_q7, 7, "q7", 0, 1, 0, 0, 0, 0, 0, 1) \
183 X(Reg_q8, 8, "q8", 1, 0, 0, 0, 0, 0, 0, 1) \
184 X(Reg_q9, 9, "q9", 1, 0, 0, 0, 0, 0, 0, 1) \
185 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 1) \
186 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 1) \
187 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 1) \
188 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 1) \
189 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 1) \
190 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 1)
191 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
192 // isInt, isFP32, isFP64, isVec128)
53 193
54 // We also provide a combined table, so that there is a namespace where 194 // We also provide a combined table, so that there is a namespace where
55 // all of the registers are considered and have distinct numberings. 195 // all of the registers are considered and have distinct numberings.
56 // This is in contrast to the above, where the "encode" is based on how 196 // This is in contrast to the above, where the "encode" is based on how
57 // the register numbers will be encoded in binaries and values can overlap. 197 // the register numbers will be encoded in binaries and values can overlap.
58 #define REGARM32_TABLE \ 198 #define REGARM32_TABLE \
59 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, isFP */ \ 199 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
60 REGARM32_GPR_TABLE 200 isFP32, isFP64, isVec128 */ \
61 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 201 REGARM32_GPR_TABLE \
62 // isInt, isFP) 202 REGARM32_FP32_TABLE \
63 203 REGARM32_FP64_TABLE \
64 #define REGARM32_TABLE_BOUNDS \ 204 REGARM32_VEC128_TABLE
65 /* val, init */ \ 205 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
66 X(Reg_GPR_First, = Reg_r0) \ 206 // isInt, isFP32, isFP64, isVec128)
67 X(Reg_GPR_Last, = Reg_pc) 207
68 //define X(val, init) 208 #define REGARM32_TABLE_BOUNDS \
69 209 /* val, init */ \
70 // TODO(jvoung): add condition code tables, etc. 210 X(Reg_GPR_First, = Reg_r0) \
71 211 X(Reg_GPR_Last, = Reg_pc) \
72 // Load/Store instruction width suffixes. 212 X(Reg_SREG_First, = Reg_s0) \
73 #define ICETYPEARM32_TABLE \ 213 X(Reg_SREG_Last, = Reg_s31) \
74 /* tag, element type, width, addr off bits sext, zext */ \ 214 X(Reg_DREG_First, = Reg_d0) \
75 X(IceType_void, IceType_void, "", 0, 0) \ 215 X(Reg_DREG_Last, = Reg_d31) \
76 X(IceType_i1, IceType_void, "b", 8, 12) \ 216 X(Reg_QREG_First, = Reg_q0) \
77 X(IceType_i8, IceType_void, "b", 8, 12) \ 217 X(Reg_QREG_Last, = Reg_q15)
78 X(IceType_i16, IceType_void, "h", 8, 8) \ 218 // define X(val, init)
79 X(IceType_i32, IceType_void, "", 12, 12) \ 219
80 X(IceType_i64, IceType_void, "d", 8, 8) \ 220 // Load/Store instruction width suffixes and FP/Vector element size suffixes
81 X(IceType_f32, IceType_void, "", 10, 10) \ 221 // the # of offset bits allowed as part of an addressing mode (for sign or
82 X(IceType_f64, IceType_void, "", 10, 10) \ 222 // zero extending load/stores).
83 X(IceType_v4i1, IceType_i32 , "", 0, 0) \ 223 #define ICETYPEARM32_TABLE \
84 X(IceType_v8i1, IceType_i16 , "", 0, 0) \ 224 /* tag, element type, int_width, vec_width, addr bits sext, zext */ \
85 X(IceType_v16i1, IceType_i8 , "", 0, 0) \ 225 X(IceType_void, IceType_void, "", "", 0, 0) \
86 X(IceType_v16i8, IceType_i8 , "", 0, 0) \ 226 X(IceType_i1, IceType_void, "b", "", 8, 12) \
87 X(IceType_v8i16, IceType_i16 , "", 0, 0) \ 227 X(IceType_i8, IceType_void, "b", "", 8, 12) \
88 X(IceType_v4i32, IceType_i32 , "", 0, 0) \ 228 X(IceType_i16, IceType_void, "h", "", 8, 8) \
89 X(IceType_v4f32, IceType_f32 , "", 0, 0) \ 229 X(IceType_i32, IceType_void, "", "", 12, 12) \
90 //#define X(tag, elementty, width, sbits, ubits) 230 X(IceType_i64, IceType_void, "d", "", 8, 8) \
231 X(IceType_f32, IceType_void, "", ".f32", 10, 10) \
232 X(IceType_f64, IceType_void, "", ".f64", 10, 10) \
233 X(IceType_v4i1, IceType_i32, "", ".i32", 0, 0) \
234 X(IceType_v8i1, IceType_i16, "", ".i16", 0, 0) \
235 X(IceType_v16i1, IceType_i8, "", ".i8", 0, 0) \
236 X(IceType_v16i8, IceType_i8, "", ".i8", 0, 0) \
237 X(IceType_v8i16, IceType_i16, "", ".i16", 0, 0) \
238 X(IceType_v4i32, IceType_i32, "", ".i32", 0, 0) \
239 X(IceType_v4f32, IceType_f32, "", ".f32", 0, 0)
240 //#define X(tag, elementty, int_width, vec_width, sbits, ubits)
91 241
92 // Shifter types for Data-processing operands as defined in section A5.1.2. 242 // Shifter types for Data-processing operands as defined in section A5.1.2.
93 #define ICEINSTARM32SHIFT_TABLE \ 243 #define ICEINSTARM32SHIFT_TABLE \
94 /* enum value, emit */ \ 244 /* enum value, emit */ \
95 X(LSL, "lsl") \ 245 X(LSL, "lsl") \
96 X(LSR, "lsr") \ 246 X(LSR, "lsr") \
97 X(ASR, "asr") \ 247 X(ASR, "asr") \
98 X(ROR, "ror") \ 248 X(ROR, "ror") \
99 X(RRX, "rrx") \ 249 X(RRX, "rrx")
100 //#define X(tag, emit) 250 //#define X(tag, emit)
101 251
102 // Attributes for the condition code 4-bit encoding (that is independent 252 // Attributes for the condition code 4-bit encoding (that is independent
103 // of the APSR's NZCV fields). For example, EQ is 0, but corresponds to 253 // of the APSR's NZCV fields). For example, EQ is 0, but corresponds to
104 // Z = 1, and NE is 1, but corresponds to Z = 0. 254 // Z = 1, and NE is 1, but corresponds to Z = 0.
105 #define ICEINSTARM32COND_TABLE \ 255 #define ICEINSTARM32COND_TABLE \
106 /* enum value, encoding, opposite, emit */ \ 256 /* enum value, encoding, opposite, emit */ \
107 X(EQ, 0, NE, "eq") /* equal */ \ 257 X(EQ, 0, NE, "eq") /* equal */ \
108 X(NE, 1, EQ, "ne") /* not equal */ \ 258 X(NE, 1, EQ, "ne") /* not equal */ \
109 X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \ 259 X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \
110 X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \ 260 X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \
111 X(MI, 4, PL, "mi") /* minus/negative */ \ 261 X(MI, 4, PL, "mi") /* minus/negative */ \
112 X(PL, 5, MI, "pl") /* plus/positive or zero */ \ 262 X(PL, 5, MI, "pl") /* plus/positive or zero */ \
113 X(VS, 6, VC, "vs") /* overflow (float unordered) */ \ 263 X(VS, 6, VC, "vs") /* overflow (float unordered) */ \
114 X(VC, 7, VS, "vc") /* no overflow (float not unordered) */ \ 264 X(VC, 7, VS, "vc") /* no overflow (float not unordered) */ \
115 X(HI, 8, LS, "hi") /* unsigned higher */ \ 265 X(HI, 8, LS, "hi") /* unsigned higher */ \
116 X(LS, 9, HI, "ls") /* unsigned lower or same */ \ 266 X(LS, 9, HI, "ls") /* unsigned lower or same */ \
117 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ 267 X(GE, 10, LT, "ge") /* signed greater than or equal */ \
118 X(LT, 11, GE, "lt") /* signed less than */ \ 268 X(LT, 11, GE, "lt") /* signed less than */ \
119 X(GT, 12, LE, "gt") /* signed greater than */ \ 269 X(GT, 12, LE, "gt") /* signed greater than */ \
120 X(LE, 13, GT, "le") /* signed less than or equal */ \ 270 X(LE, 13, GT, "le") /* signed less than or equal */ \
121 X(AL, 14, kNone, "") /* always (unconditional) */ \ 271 X(AL, 14, kNone, "") /* always (unconditional) */ \
122 X(kNone, 15, kNone, "??") /* special condition / none */ \ 272 X(kNone, 15, kNone, "??") /* special condition / none */
123 //#define(tag, encode, opp, emit) 273 //#define(tag, encode, opp, emit)
124 274
125 #endif // SUBZERO_SRC_ICEINSTARM32_DEF 275 #endif // SUBZERO_SRC_ICEINSTARM32_DEF
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