MIPS64: Fix the integer division in crankshaft.

src/mips64/simulator-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "src/v8.h"
@@ skipping 3776 matching lines @@
       }
       break;
     case DMULTU:
       UNIMPLEMENTED_MIPS();
       break;
     case DSLL:
       set_register(rd_reg, alu_out);
       TraceRegWr(alu_out);
       break;
     case DIV:
-    case DDIV:
+    case DDIV: {
+      const int64_t int_min_value =
+          instr->FunctionFieldRaw() == DIV ? INT_MIN : LONG_MIN;
       switch (kArchVariant) {
         case kMips64r2:
           // Divide by zero and overflow was not checked in the
           // configuration step - div and divu do not raise exceptions. On
           // division by 0 the result will be UNPREDICTABLE. On overflow
           // (INT_MIN/-1), return INT_MIN which is what the hardware does.
-          if (rs == INT_MIN && rt == -1) {
-            set_register(LO, INT_MIN);
+          if (rs == int_min_value && rt == -1) {
+            set_register(LO, int_min_value);
             set_register(HI, 0);
           } else if (rt != 0) {
             set_register(LO, rs / rt);
             set_register(HI, rs % rt);
           }
           break;
         case kMips64r6:
           switch (instr->SaValue()) {
             case DIV_OP:
-              if (rs == INT_MIN && rt == -1) {
-                set_register(rd_reg, INT_MIN);
+              if (rs == int_min_value && rt == -1) {
+                set_register(rd_reg, int_min_value);
               } else if (rt != 0) {
                 set_register(rd_reg, rs / rt);
               }
               break;
             case MOD_OP:
-              if (rs == INT_MIN && rt == -1) {
+              if (rs == int_min_value && rt == -1) {
                 set_register(rd_reg, 0);
               } else if (rt != 0) {
                 set_register(rd_reg, rs % rt);
               }
               break;
             default:
               UNIMPLEMENTED_MIPS();
               break;
           }
           break;
         default:
           break;
       }
       break;
+    }
     case DIVU:
       if (rt_u != 0) {
         set_register(LO, rs_u / rt_u);
         set_register(HI, rs_u % rt_u);
       }
       break;
     // Break and trap instructions.
     case BREAK:
     case TGE:
     case TGEU:
@@ skipping 931 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS64