Adds branch instructions and labels to the MIPS simulator, assembler, disassembler.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 129 matching lines @@
         prologue_offset_(-1),
         delay_slot_available_(false),
         in_delay_slot_(false),
         comments_() { }
   ~Assembler() { }
 
   void PopRegister(Register r) {
     UNIMPLEMENTED();
   }
 
-  void Bind(Label* label) {
-    UNIMPLEMENTED();
-  }
+  void Bind(Label* label);
 
   // Misc. functionality
   int CodeSize() const { return buffer_.Size(); }
   int prologue_offset() const { return -1; }
   const ZoneGrowableArray<int>& GetPointerOffsets() const {
     return buffer_.pointer_offsets();
   }
   const GrowableObjectArray& object_pool() const { return object_pool_; }
   void FinalizeInstructions(const MemoryRegion& region) {
     buffer_.FinalizeInstructions(region);
@@ skipping 75 matching lines @@
   void and_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, AND);
   }
 
   void andi(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ANDI, rs, rt, imm_value);
   }
 
+  // Branch if equal.
+  void beq(Register rs, Register rt, Label* l) {
+    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.

[regis, 2013/03/22 19:51:16]

Either remove this comment or add it consistently below.

[zra, 2013/03/22 20:16:01]

Done.

+    EmitBranch(BEQ, rs, rt, l);
+    EmitBranchDelayNop();
+  }
+
+  // Branch if equal, likely taken.
+  // Delay slot executed only when branch taken.
+  void beql(Register rs, Register rt, Label* l) {
+    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
+    EmitBranch(BEQL, rs, rt, l);
+    EmitBranchDelayNop();
+  }
+
+  // Brach if rs >= 0.

[regis, 2013/03/22 19:51:16]

Branch

[zra, 2013/03/22 20:16:01]

Done.

+  void bgez(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitRegImmBranch(BGEZ, rs, l);
+    EmitBranchDelayNop();
+  }
+
+  // Branch if rs >= 0, likely taken.
+  // Delay slot executed only when branch taken.
+  void bgezl(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitRegImmBranch(BGEZL, rs, l);
+    EmitBranchDelayNop();
+  }
+
+  // Brach if rs > 0.

[regis, 2013/03/22 19:51:16]

Branch

[zra, 2013/03/22 20:16:01]

Done.

+  void bgtz(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitBranch(BGTZ, rs, R0, l);
+    EmitBranchDelayNop();
+  }
+
+  // Branch if rs > 0, likely taken.
+  // Delay slot executed only when branch taken.
+  void bgtzl(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitBranch(BGTZL, rs, R0, l);
+    EmitBranchDelayNop();
+  }
+
+  // Brach if rs <= 0.

[regis, 2013/03/22 19:51:16]

Branch

[zra, 2013/03/22 20:16:01]

Done.

+  void blez(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitBranch(BLEZ, rs, R0, l);
+    EmitBranchDelayNop();
+  }
+
+  // Branch if rs <= 0, likely taken.
+  // Delay slot executed only when branch taken.
+  void blezl(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitBranch(BLEZL, rs, R0, l);
+    EmitBranchDelayNop();
+  }
+
+  // Brach if rs < 0.

[regis, 2013/03/22 19:51:16]

Branch

[zra, 2013/03/22 20:16:01]

Done.

+  void bltz(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitRegImmBranch(BLTZ, rs, l);
+    EmitBranchDelayNop();
+  }
+
+  // Branch if rs < 0, likely taken.
+  // Delay slot executed only when branch taken.
+  void bltzl(Register rs, Label* l) {
+    ASSERT(!in_delay_slot_);
+    EmitRegImmBranch(BLTZL, rs, l);
+    EmitBranchDelayNop();
+  }
+
+  // Branch if not equal.
+  void bne(Register rs, Register rt, Label* l) {
+    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
+    EmitBranch(BNE, rs, rt, l);
+    EmitBranchDelayNop();
+  }
+
+  // Branch if not equal, likely taken.
+  // Delay slot executed only when branch taken.
+  void bnel(Register rs, Register rt, Label* l) {
+    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
+    EmitBranch(BNEL, rs, rt, l);
+    EmitBranchDelayNop();
+  }
+
   void break_(int32_t code) {
     ASSERT(Utils::IsUint(20, code));
     Emit(SPECIAL << kOpcodeShift |
          code << kBreakCodeShift |
          BREAK << kFunctionShift);
   }
 
   void clo(Register rd, Register rs) {
     EmitRType(SPECIAL2, rs, rd, rd, 0, CLO);
   }
@@ skipping 137 matching lines @@
 
   void sw(Register rt, const Address& addr) {
     EmitLoadStore(SW, rt, addr);
   }
 
   void xor_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, XOR);
   }
 
   // Macros in alphabetical order.
+
+  // Unconditional branch.
+  void B(Label* l) {

[regis, 2013/03/22 19:51:16]

I would use a lower case 'b', since the MIPS assembler understands it. It is not
really our own macro, and it maps to a single instruction. It is more like a
pseudo instruction than a macro.

[zra, 2013/03/22 20:16:01]

That makes sense. I've made it lowercase and moved it up out of the Macros
section.

+    beq(R0, R0, l);
+  }
+
   void LoadImmediate(Register rd, int32_t value) {
     if (Utils::IsInt(16, value)) {
       addiu(rd, ZR, Immediate(value));
     } else {
       lui(rd, Immediate((value >> 16) & 0xffff));
       ori(rd, rd, Immediate(value & 0xffff));
     }
   }
 
   void Move(Register rd, Register rs) {

[regis, 2013/03/22 19:51:16]

This one is debatable, but this is also a pseudo instruction. We should use
'mov' for readability, since we have movn, movz, movt, etc.. But either way is
fine with me.

[zra, 2013/03/22 20:16:01]

I've made it mov, and moved it up, too, since mov is also how it is
disassembled.

     or_(rd, rs, ZR);
   }
 
+  void Nop() {

[regis, 2013/03/22 19:51:16]

nop?

[zra, 2013/03/22 20:16:01]

Same as with mov.

+    Emit(Instr::kNopInstruction);
+  }
+
  private:
   AssemblerBuffer buffer_;
   GrowableObjectArray& object_pool_;  // Objects and patchable jump targets.
   int prologue_offset_;
 
   bool delay_slot_available_;
   bool in_delay_slot_;
 
   class CodeComment : public ZoneAllocated {
    public:
@@ skipping 61 matching lines @@
                  SpecialFunction func) {
     ASSERT(Utils::IsUint(5, sa));
     Emit(opcode << kOpcodeShift |
          rs << kRsShift |
          rt << kRtShift |
          rd << kRdShift |
          sa << kSaShift |
          func << kFunctionShift);
   }
 
+  void EmitBranch(Opcode b, Register rs, Register rt, Label* label) {
+    if (label->IsBound()) {
+      uint16_t dest = EncodeBranchOffset(label->Position() - buffer_.Size(), 0);
+      EmitIType(b, rs, rt, dest);
+    } else {
+      int position = buffer_.Size();
+      EmitIType(b, rs, rt, label->position_);
+      label->LinkTo(position);
+    }
+  }
+
+  void EmitRegImmBranch(RtRegImm b, Register rs, Label* label) {
+    if (label->IsBound()) {
+      uint16_t dest = EncodeBranchOffset(label->Position() - buffer_.Size(), 0);
+      EmitRegImmType(REGIMM, rs, b, dest);
+    } else {
+      int position = buffer_.Size();
+      EmitRegImmType(REGIMM, rs, b, label->position_);
+      label->LinkTo(position);
+    }
+  }
+
+  static int32_t EncodeBranchOffset(int32_t offset, int32_t inst);

[regis, 2013/03/22 19:51:16]

inst -> instr

[zra, 2013/03/22 20:16:01]

Done.

+  static int DecodeBranchOffset(int32_t inst);

[regis, 2013/03/22 19:51:16]

inst -> instr

[zra, 2013/03/22 20:16:01]

Done.

+
   void EmitBranchDelayNop() {
     Emit(Instr::kNopInstruction);  // Branch delay NOP.
     delay_slot_available_ = true;
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_