- Allow the use of branch delay slots.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 115 matching lines @@
   }
 };
 
 
 class Assembler : public ValueObject {
  public:
   Assembler()
       : buffer_(),
         object_pool_(GrowableObjectArray::Handle()),
         prologue_offset_(-1),
+        delay_slot_available_(false),
+        in_delay_slot_(false),
         comments_() { }
   ~Assembler() { }
 
   void PopRegister(Register r) {
     UNIMPLEMENTED();
   }
 
   void Bind(Label* label) {
     UNIMPLEMENTED();
   }
@@ skipping 53 matching lines @@
   static const char* RegisterName(Register reg) {
     UNIMPLEMENTED();
     return NULL;
   }
 
   static const char* FpuRegisterName(FpuRegister reg) {
     UNIMPLEMENTED();
     return NULL;
   }
 
+  // A utility to be able to assemble an instruction into the delay slot.
+  Assembler* delay_slot() {
+    ASSERT(delay_slot_available_);
+    ASSERT(buffer_.Load<int32_t>(buffer_.GetPosition() - sizeof(int32_t)) ==
+        Instr::kNopInstruction);
+    buffer_.Backup<int32_t>();
+    delay_slot_available_ = false;
+    in_delay_slot_ = true;
+    return this;
+  }
+
   // CPU instructions.
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
   void jr(Register rs) {
+    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, R0, 0, JR);
-    Emit(0);  // Branch delay NOP.
+    Emit(Instr::kNopInstruction);  // Branch delay NOP.
+    delay_slot_available_ = true;
   }
 
  private:
   AssemblerBuffer buffer_;
   GrowableObjectArray& object_pool_;  // Objects and patchable jump targets.
   int prologue_offset_;
 
+  bool delay_slot_available_;
+  bool in_delay_slot_;
+
   class CodeComment : public ZoneAllocated {
    public:
     CodeComment(intptr_t pc_offset, const String& comment)
         : pc_offset_(pc_offset), comment_(comment) { }
 
     intptr_t pc_offset() const { return pc_offset_; }
     const String& comment() const { return comment_; }
 
    private:
     intptr_t pc_offset_;
     const String& comment_;
 
     DISALLOW_COPY_AND_ASSIGN(CodeComment);
   };
 
   GrowableArray<CodeComment*> comments_;
 
   void Emit(int32_t value) {
+    in_delay_slot_ = false;
     AssemblerBuffer::EnsureCapacity ensured(&buffer_);
     buffer_.Emit<int32_t>(value);
   }
 
   // Encode CPU instructions according to the types specified in
   // Figures 4-1, 4-2 and 4-3 in VolI-A.
   void EmitIType(Opcode opcode,
                  Register rs,
                  Register rt,
                  uint16_t imm) {
@@ skipping 22 matching lines @@
          func << kFunctionShift);
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_