Introduce the ability to insert IACA (Intel Architecture Code Analyzer) marks to

src/IceInstX86Base.h

 //===- subzero/src/IceInstX86Base.h - Generic x86 instructions -*- C++ -*--===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 114 matching lines @@
     Sub,
     SubRMW,
     Subps,
     Subss,
     Test,
     Ucomiss,
     UD2,
     Xadd,
     Xchg,
     Xor,
-    XorRMW
+    XorRMW,
+
+    /// Intel Architecture Code Analyzer markers. These are not executable so
+    /// must only be used for analysis.
+    IacaStart,
+    IacaEnd
   };
 
   static const char *getWidthString(Type Ty);
   static const char *getFldString(Type Ty);
   static typename Traits::Cond::BrCond
   getOppositeCondition(typename Traits::Cond::BrCond Cond);
   void dump(const Cfg *Func) const override;
 
   // Shared emit routines for common forms of instructions.
   // See the definition of emitTwoAddress() for a description of
@@ skipping 2541 matching lines @@
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) {
     return InstX86Base<Machine>::isClassof(Inst, InstX86Base<Machine>::Xchg);
   }
 
 private:
   InstX86Xchg(Cfg *Func, Operand *Dest, Variable *Source);
 };
 
+/// Start marker for the Intel Architecture Code Analyzer. This is not an
+/// executable instruction and must only be used for analysis.
+template <class Machine>
+class InstX86IacaStart final : public InstX86Base<Machine> {
+  InstX86IacaStart() = delete;
+  InstX86IacaStart(const InstX86IacaStart &) = delete;
+  InstX86IacaStart &operator=(const InstX86IacaStart &) = delete;
+
+public:
+  static InstX86IacaStart *create(Cfg *Func) {
+    return new (Func->allocate<InstX86IacaStart>()) InstX86IacaStart(Func);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) {
+    return InstX86Base<Machine>::isClassof(Inst,
+                                           InstX86Base<Machine>::IacaStart);
+  }
+
+private:
+  InstX86IacaStart(Cfg *Func);
+};
+
+/// End marker for the Intel Architecture Code Analyzer. This is not an
+/// executable instruction and must only be used for analysis.
+template <class Machine>
+class InstX86IacaEnd final : public InstX86Base<Machine> {
+  InstX86IacaEnd() = delete;
+  InstX86IacaEnd(const InstX86IacaEnd &) = delete;
+  InstX86IacaEnd &operator=(const InstX86IacaEnd &) = delete;
+
+public:
+  static InstX86IacaEnd *create(Cfg *Func) {
+    return new (Func->allocate<InstX86IacaEnd>()) InstX86IacaEnd(Func);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) {
+    return InstX86Base<Machine>::isClassof(Inst, InstX86Base<Machine>::IacaEnd);
+  }
+
+private:
+  InstX86IacaEnd(Cfg *Func);
+};
+
 /// struct Insts is a template that can be used to instantiate all the X86
 /// instructions for a target with a simple
 ///
 /// using Insts = ::Ice::X86Internal::Insts<TargeT>;
 template <class Machine> struct Insts {
   using FakeRMW = InstX86FakeRMW<Machine>;
   using Label = InstX86Label<Machine>;
 
   using AdjustStack = InstX86AdjustStack<Machine>;
   using Call = InstX86Call<Machine>;
@@ skipping 84 matching lines @@
   template <typename T = typename InstX86Base<Machine>::Traits>
   using Fld = typename std::enable_if<T::UsesX87, InstX86Fld<Machine>>::type;
   template <typename T = typename InstX86Base<Machine>::Traits>
   using Fstp = typename std::enable_if<T::UsesX87, InstX86Fstp<Machine>>::type;
   using Pop = InstX86Pop<Machine>;
   using Push = InstX86Push<Machine>;
   using Ret = InstX86Ret<Machine>;
   using Setcc = InstX86Setcc<Machine>;
   using Xadd = InstX86Xadd<Machine>;
   using Xchg = InstX86Xchg<Machine>;
+
+  using IacaStart = InstX86IacaStart<Machine>;
+  using IacaEnd = InstX86IacaEnd<Machine>;
 };
 
 /// X86 Instructions have static data (particularly, opcodes and instruction
 /// emitters). Each X86 target needs to define all of these, so this macro is
 /// provided so that, if something changes, then all X86 targets will be updated
 /// automatically.
 #define X86INSTS_DEFINE_STATIC_DATA(Machine)                                   \
   namespace Ice {                                                              \
   namespace X86Internal {                                                      \
   /* In-place ops */                                                           \
@@ skipping 338 matching lines @@
           &InstX86Base<Machine>::Traits::Assembler::psrl};                     \
   }                                                                            \
   }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceInstX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICEINSTX86BASE_H