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Side by Side Diff: src/IceAssemblerX86Base.h

Issue 1260093003: Introduce the ability to insert IACA (Intel Architecture Code Analyzer) marks to (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 4 months ago
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1 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===// 1 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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825 825
826 void lock(); 826 void lock();
827 void cmpxchg(Type Ty, const typename Traits::Address &address, 827 void cmpxchg(Type Ty, const typename Traits::Address &address,
828 typename Traits::GPRRegister reg, bool Locked); 828 typename Traits::GPRRegister reg, bool Locked);
829 void cmpxchg8b(const typename Traits::Address &address, bool Locked); 829 void cmpxchg8b(const typename Traits::Address &address, bool Locked);
830 void xadd(Type Ty, const typename Traits::Address &address, 830 void xadd(Type Ty, const typename Traits::Address &address,
831 typename Traits::GPRRegister reg, bool Locked); 831 typename Traits::GPRRegister reg, bool Locked);
832 void xchg(Type Ty, const typename Traits::Address &address, 832 void xchg(Type Ty, const typename Traits::Address &address,
833 typename Traits::GPRRegister reg); 833 typename Traits::GPRRegister reg);
834 834
835 /// \name Intel Architecture Code Analyzer markers.
836 /// @{
837 void iaca_start();
838 void iaca_end();
839 /// @}
840
835 void emitSegmentOverride(uint8_t prefix); 841 void emitSegmentOverride(uint8_t prefix);
836 842
837 intptr_t preferredLoopAlignment() { return 16; } 843 intptr_t preferredLoopAlignment() { return 16; }
838 void align(intptr_t alignment, intptr_t offset); 844 void align(intptr_t alignment, intptr_t offset);
839 void bind(Label *label); 845 void bind(Label *label);
840 846
841 intptr_t CodeSize() const { return Buffer.size(); } 847 intptr_t CodeSize() const { return Buffer.size(); }
842 848
843 protected: 849 protected:
844 inline void emitUint8(uint8_t value); 850 inline void emitUint8(uint8_t value);
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1038 emitUint8(0x66); 1044 emitUint8(0x66);
1039 } 1045 }
1040 1046
1041 } // end of namespace X86Internal 1047 } // end of namespace X86Internal
1042 1048
1043 } // end of namespace Ice 1049 } // end of namespace Ice
1044 1050
1045 #include "IceAssemblerX86BaseImpl.h" 1051 #include "IceAssemblerX86BaseImpl.h"
1046 1052
1047 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H 1053 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H
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