Iasm and obj lowering for advanced switch lowering.

tests_lit/llvm2ice_tests/switch-opt.ll

 ; This tests a switch statement, including multiple branches to the
 ; same label which also results in phi instructions with multiple
 ; entries for the same incoming edge.
 
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
+; For x86 see adv-switch-lowering.ll

[Jim Stichnoth, 2015/07/30 15:20:24]

adv-switch-opt.ll

[ascull, 2015/07/30 17:30:00]

Done.

 
 ; TODO(jvoung): Update to -02 once the phi assignments is done for ARM
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble --disassemble \
 ; RUN:   --target arm32 -i %s --args -Om1 --skip-unimplemented \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:     --command FileCheck --check-prefix ARM32 %s
 
 define i32 @testSwitch(i32 %a) {
 entry:
@@ skipping 30 matching lines @@
 ; register.
 define i32 @testSwitchImm() {
 entry:
   switch i32 10, label %sw.default [
     i32 1, label %sw.default
   ]
 
 sw.default:
   ret i32 20
 }
-; CHECK-LABEL: testSwitchImm
-; CHECK-NOT: cmp 0x{{[0-9a-f]*}},
-
 ; ARM32-LABEL: testSwitchImm
 ; ARM32: cmp {{r[0-9]+}}, #1
 ; ARM32-NEXT: beq
 ; ARM32-NEXT: b
 
 ; Test for correct 64-bit lowering.
 define internal i32 @testSwitch64(i64 %a) {
 entry:
   switch i64 %a, label %sw.default [
     i64 123, label %return
@@ skipping 11 matching lines @@
 sw.bb3:                                           ; preds = %entry
   br label %return
 
 sw.default:                                       ; preds = %entry
   br label %return
 
 return:                                           ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %entry
   %retval.0 = phi i32 [ 5, %sw.default ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %entry ]
   ret i32 %retval.0
 }
-; CHECK-LABEL: testSwitch64
-; CHECK: cmp {{.*}},0x7b
-; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}},0x0
-; CHECK-NEXT: je
-; CHECK: cmp {{.*}},0xea
-; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}},0x0
-; CHECK-NEXT: je
-; CHECK: cmp {{.*}},0x159
-; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}},0x0
-; CHECK-NEXT: je
-; CHECK: cmp {{.*}},0x34567890
-; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}},0x12
-; CHECK-NEXT: je
-
 ; ARM32-LABEL: testSwitch64
 ; ARM32: cmp {{r[0-9]+}}, #123
 ; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
 ; ARM32-NEXT: beq
 ; ARM32: cmp {{r[0-9]+}}, #234
 ; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
 ; ARM32-NEXT: beq
 ; ARM32: movw [[REG:r[0-9]+]], #345
 ; ARM32-NEXT: cmp {{r[0-9]+}}, [[REG]]
 ; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
@@ skipping 10 matching lines @@
 ; assembler.
 define i32 @testSwitchImm64() {
 entry:
   switch i64 10, label %sw.default [
     i64 1, label %sw.default
   ]
 
 sw.default:
   ret i32 20
 }
-; CHECK-LABEL: testSwitchImm64
-; CHECK: cmp {{.*}},0x1
-; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}},0x0
-; CHECK-NEXT: je
-
 ; ARM32-LABEL: testSwitchImm64
 ; ARM32: cmp {{r[0-9]+}}, #1
 ; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
 ; ARM32-NEXT: beq [[ADDR:[0-9a-f]+]]
 ; ARM32-NEXT: b [[ADDR]]
 
 define i32 @testSwitchUndef64() {
 entry:
   switch i64 undef, label %sw.default [
     i64 1, label %sw.default
   ]
 
 sw.default:
   ret i32 20
 }
-; CHECK-LABEL: testSwitchUndef64
-; CHECK: mov {{.*}},0x0
-; CHECK: mov {{.*}},0x0
 ; ARM32-LABEL: testSwitchUndef64
 ; ARM32: movw {{.*}}, #0
 ; ARM32: movw {{.*}}, #0