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Side by Side Diff: src/mips64/macro-assembler-mips64.h

Issue 1255883002: VectorICs: vector [keyed]store ic MISS handling infrastructure. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix nit. Created 5 years, 4 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 #include "src/mips64/assembler-mips64.h" 10 #include "src/mips64/assembler-mips64.h"
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692 692
693 // Push four registers. Pushes leftmost register first (to highest address). 693 // Push four registers. Pushes leftmost register first (to highest address).
694 void Push(Register src1, Register src2, Register src3, Register src4) { 694 void Push(Register src1, Register src2, Register src3, Register src4) {
695 Dsubu(sp, sp, Operand(4 * kPointerSize)); 695 Dsubu(sp, sp, Operand(4 * kPointerSize));
696 sd(src1, MemOperand(sp, 3 * kPointerSize)); 696 sd(src1, MemOperand(sp, 3 * kPointerSize));
697 sd(src2, MemOperand(sp, 2 * kPointerSize)); 697 sd(src2, MemOperand(sp, 2 * kPointerSize));
698 sd(src3, MemOperand(sp, 1 * kPointerSize)); 698 sd(src3, MemOperand(sp, 1 * kPointerSize));
699 sd(src4, MemOperand(sp, 0 * kPointerSize)); 699 sd(src4, MemOperand(sp, 0 * kPointerSize));
700 } 700 }
701 701
702 // Push five registers. Pushes leftmost register first (to highest address).
703 void Push(Register src1, Register src2, Register src3, Register src4,
704 Register src5) {
705 Dsubu(sp, sp, Operand(5 * kPointerSize));
706 sd(src1, MemOperand(sp, 4 * kPointerSize));
707 sd(src2, MemOperand(sp, 3 * kPointerSize));
708 sd(src3, MemOperand(sp, 2 * kPointerSize));
709 sd(src4, MemOperand(sp, 1 * kPointerSize));
710 sd(src5, MemOperand(sp, 0 * kPointerSize));
711 }
712
702 void Push(Register src, Condition cond, Register tst1, Register tst2) { 713 void Push(Register src, Condition cond, Register tst1, Register tst2) {
703 // Since we don't have conditional execution we use a Branch. 714 // Since we don't have conditional execution we use a Branch.
704 Branch(3, cond, tst1, Operand(tst2)); 715 Branch(3, cond, tst1, Operand(tst2));
705 Dsubu(sp, sp, Operand(kPointerSize)); 716 Dsubu(sp, sp, Operand(kPointerSize));
706 sd(src, MemOperand(sp, 0)); 717 sd(src, MemOperand(sp, 0));
707 } 718 }
708 719
709 void PushRegisterAsTwoSmis(Register src, Register scratch = at); 720 void PushRegisterAsTwoSmis(Register src, Register scratch = at);
710 void PopRegisterAsTwoSmis(Register dst, Register scratch = at); 721 void PopRegisterAsTwoSmis(Register dst, Register scratch = at);
711 722
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1818 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x) 1829 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x)
1819 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 1830 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
1820 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 1831 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
1821 #else 1832 #else
1822 #define ACCESS_MASM(masm) masm-> 1833 #define ACCESS_MASM(masm) masm->
1823 #endif 1834 #endif
1824 1835
1825 } } // namespace v8::internal 1836 } } // namespace v8::internal
1826 1837
1827 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 1838 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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