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Issue 1255883002: VectorICs: vector [keyed]store ic MISS handling infrastructure. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix nit. Created 5 years, 4 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/v8.h" 5 #include "src/v8.h"
6 6
7 #if V8_TARGET_ARCH_X64 7 #if V8_TARGET_ARCH_X64
8 8
9 #include "src/codegen.h" 9 #include "src/codegen.h"
10 #include "src/ic/ic.h" 10 #include "src/ic/ic.h"
(...skipping 735 matching lines...) Expand 10 before | Expand all | Expand 10 after
746 746
747 // Cache miss: Jump to runtime. 747 // Cache miss: Jump to runtime.
748 GenerateMiss(masm); 748 GenerateMiss(masm);
749 } 749 }
750 750
751 751
752 static void StoreIC_PushArgs(MacroAssembler* masm) { 752 static void StoreIC_PushArgs(MacroAssembler* masm) {
753 Register receiver = StoreDescriptor::ReceiverRegister(); 753 Register receiver = StoreDescriptor::ReceiverRegister();
754 Register name = StoreDescriptor::NameRegister(); 754 Register name = StoreDescriptor::NameRegister();
755 Register value = StoreDescriptor::ValueRegister(); 755 Register value = StoreDescriptor::ValueRegister();
756 Register temp = r11;
757 DCHECK(!temp.is(receiver) && !temp.is(name) && !temp.is(value));
756 758
757 DCHECK(!rbx.is(receiver) && !rbx.is(name) && !rbx.is(value)); 759 __ PopReturnAddressTo(temp);
758
759 __ PopReturnAddressTo(rbx);
760 __ Push(receiver); 760 __ Push(receiver);
761 __ Push(name); 761 __ Push(name);
762 __ Push(value); 762 __ Push(value);
763 __ PushReturnAddressFrom(rbx); 763 if (FLAG_vector_stores) {
764 Register slot = VectorStoreICDescriptor::SlotRegister();
765 Register vector = VectorStoreICDescriptor::VectorRegister();
766 DCHECK(!temp.is(slot) && !temp.is(vector));
767 __ Push(slot);
768 __ Push(vector);
769 }
770 __ PushReturnAddressFrom(temp);
764 } 771 }
765 772
766 773
767 void StoreIC::GenerateMiss(MacroAssembler* masm) { 774 void StoreIC::GenerateMiss(MacroAssembler* masm) {
768 // Return address is on the stack. 775 // Return address is on the stack.
769 StoreIC_PushArgs(masm); 776 StoreIC_PushArgs(masm);
770 777
771 // Perform tail call to the entry. 778 // Perform tail call to the entry.
772 __ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1); 779 int args = FLAG_vector_stores ? 5 : 3;
780 __ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1);
773 } 781 }
774 782
775 783
776 void StoreIC::GenerateNormal(MacroAssembler* masm) { 784 void StoreIC::GenerateNormal(MacroAssembler* masm) {
777 Register receiver = StoreDescriptor::ReceiverRegister(); 785 Register receiver = StoreDescriptor::ReceiverRegister();
778 Register name = StoreDescriptor::NameRegister(); 786 Register name = StoreDescriptor::NameRegister();
779 Register value = StoreDescriptor::ValueRegister(); 787 Register value = StoreDescriptor::ValueRegister();
780 Register dictionary = rbx; 788 Register dictionary = rbx;
781 789
782 Label miss; 790 Label miss;
783 791
784 __ movp(dictionary, FieldOperand(receiver, JSObject::kPropertiesOffset)); 792 __ movp(dictionary, FieldOperand(receiver, JSObject::kPropertiesOffset));
785 GenerateDictionaryStore(masm, &miss, dictionary, name, value, r8, r9); 793 GenerateDictionaryStore(masm, &miss, dictionary, name, value, r8, r9);
786 Counters* counters = masm->isolate()->counters(); 794 Counters* counters = masm->isolate()->counters();
787 __ IncrementCounter(counters->store_normal_hit(), 1); 795 __ IncrementCounter(counters->store_normal_hit(), 1);
788 __ ret(0); 796 __ ret(0);
789 797
790 __ bind(&miss); 798 __ bind(&miss);
791 __ IncrementCounter(counters->store_normal_miss(), 1); 799 __ IncrementCounter(counters->store_normal_miss(), 1);
792 GenerateMiss(masm); 800 GenerateMiss(masm);
793 } 801 }
794 802
795 803
796 void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) { 804 void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
797 // Return address is on the stack. 805 // Return address is on the stack.
798 StoreIC_PushArgs(masm); 806 StoreIC_PushArgs(masm);
799 807
800 // Do tail-call to runtime routine. 808 // Do tail-call to runtime routine.
801 __ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1); 809 int args = FLAG_vector_stores ? 5 : 3;
810 __ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, args, 1);
802 } 811 }
803 812
804 813
805 #undef __ 814 #undef __
806 815
807 816
808 Condition CompareIC::ComputeCondition(Token::Value op) { 817 Condition CompareIC::ComputeCondition(Token::Value op) {
809 switch (op) { 818 switch (op) {
810 case Token::EQ_STRICT: 819 case Token::EQ_STRICT:
811 case Token::EQ: 820 case Token::EQ:
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869 Condition cc = 878 Condition cc =
870 (check == ENABLE_INLINED_SMI_CHECK) 879 (check == ENABLE_INLINED_SMI_CHECK)
871 ? (*jmp_address == Assembler::kJncShortOpcode ? not_zero : zero) 880 ? (*jmp_address == Assembler::kJncShortOpcode ? not_zero : zero)
872 : (*jmp_address == Assembler::kJnzShortOpcode ? not_carry : carry); 881 : (*jmp_address == Assembler::kJnzShortOpcode ? not_carry : carry);
873 *jmp_address = static_cast<byte>(Assembler::kJccShortPrefix | cc); 882 *jmp_address = static_cast<byte>(Assembler::kJccShortPrefix | cc);
874 } 883 }
875 } // namespace internal 884 } // namespace internal
876 } // namespace v8 885 } // namespace v8
877 886
878 #endif // V8_TARGET_ARCH_X64 887 #endif // V8_TARGET_ARCH_X64
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