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1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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393 | 393 |
394 // Stack frame mapping. | 394 // Stack frame mapping. |
395 Func->genFrame(); | 395 Func->genFrame(); |
396 if (Func->hasError()) | 396 if (Func->hasError()) |
397 return; | 397 return; |
398 Func->dump("After stack frame mapping"); | 398 Func->dump("After stack frame mapping"); |
399 | 399 |
400 Func->contractEmptyNodes(); | 400 Func->contractEmptyNodes(); |
401 Func->reorderNodes(); | 401 Func->reorderNodes(); |
402 | 402 |
| 403 // Shuffle basic block order if -reorder-basic-blocks is enabled. |
| 404 Func->shuffleNodes(); |
| 405 |
403 // Branch optimization. This needs to be done just before code emission. In | 406 // Branch optimization. This needs to be done just before code emission. In |
404 // particular, no transformations that insert or reorder CfgNodes should be | 407 // particular, no transformations that insert or reorder CfgNodes should be |
405 // done after branch optimization. We go ahead and do it before nop insertion | 408 // done after branch optimization. We go ahead and do it before nop insertion |
406 // to reduce the amount of work needed for searching for opportunities. | 409 // to reduce the amount of work needed for searching for opportunities. |
407 Func->doBranchOpt(); | 410 Func->doBranchOpt(); |
408 Func->dump("After branch optimization"); | 411 Func->dump("After branch optimization"); |
409 | 412 |
410 // Nop insertion | 413 // Nop insertion if -nop-insertion is enabled. |
411 if (Ctx->getFlags().shouldDoNopInsertion()) | 414 Func->doNopInsertion(); |
412 Func->doNopInsertion(); | |
413 | 415 |
414 // Mark nodes that require sandbox alignment | 416 // Mark nodes that require sandbox alignment |
415 if (Ctx->getFlags().getUseSandboxing()) | 417 if (Ctx->getFlags().getUseSandboxing()) |
416 Func->markNodesForSandboxing(); | 418 Func->markNodesForSandboxing(); |
417 } | 419 } |
418 | 420 |
419 template <class Machine> void TargetX86Base<Machine>::translateOm1() { | 421 template <class Machine> void TargetX86Base<Machine>::translateOm1() { |
420 TimerMarker T(TimerStack::TT_Om1, Func); | 422 TimerMarker T(TimerStack::TT_Om1, Func); |
421 | 423 |
422 Func->placePhiLoads(); | 424 Func->placePhiLoads(); |
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439 regAlloc(RAK_InfOnly); | 441 regAlloc(RAK_InfOnly); |
440 if (Func->hasError()) | 442 if (Func->hasError()) |
441 return; | 443 return; |
442 Func->dump("After regalloc of infinite-weight variables"); | 444 Func->dump("After regalloc of infinite-weight variables"); |
443 | 445 |
444 Func->genFrame(); | 446 Func->genFrame(); |
445 if (Func->hasError()) | 447 if (Func->hasError()) |
446 return; | 448 return; |
447 Func->dump("After stack frame mapping"); | 449 Func->dump("After stack frame mapping"); |
448 | 450 |
449 // Nop insertion | 451 // Shuffle basic block order if -reorder-basic-blocks is enabled. |
450 if (Ctx->getFlags().shouldDoNopInsertion()) { | 452 Func->shuffleNodes(); |
451 Func->doNopInsertion(); | 453 |
452 } | 454 // Nop insertion if -nop-insertion is enabled. |
| 455 Func->doNopInsertion(); |
453 | 456 |
454 // Mark nodes that require sandbox alignment | 457 // Mark nodes that require sandbox alignment |
455 if (Ctx->getFlags().getUseSandboxing()) | 458 if (Ctx->getFlags().getUseSandboxing()) |
456 Func->markNodesForSandboxing(); | 459 Func->markNodesForSandboxing(); |
457 } | 460 } |
458 | 461 |
459 inline bool canRMW(const InstArithmetic *Arith) { | 462 inline bool canRMW(const InstArithmetic *Arith) { |
460 Type Ty = Arith->getDest()->getType(); | 463 Type Ty = Arith->getDest()->getType(); |
461 // X86 vector instructions write to a register and have no RMW option. | 464 // X86 vector instructions write to a register and have no RMW option. |
462 if (isVectorType(Ty)) | 465 if (isVectorType(Ty)) |
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5460 } | 5463 } |
5461 // the offset is not eligible for blinding or pooling, return the original | 5464 // the offset is not eligible for blinding or pooling, return the original |
5462 // mem operand | 5465 // mem operand |
5463 return MemOperand; | 5466 return MemOperand; |
5464 } | 5467 } |
5465 | 5468 |
5466 } // end of namespace X86Internal | 5469 } // end of namespace X86Internal |
5467 } // end of namespace Ice | 5470 } // end of namespace Ice |
5468 | 5471 |
5469 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 5472 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H |
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