| OLD | NEW |
| 1 ; This tests the NaCl intrinsics not related to atomic operations. | 1 ; This tests the NaCl intrinsics not related to atomic operations. |
| 2 | 2 |
| 3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ | 3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
| 4 ; RUN: --target x8632 -i %s --args -O2 -sandbox \ | 4 ; RUN: --target x8632 -i %s --args -O2 -sandbox \ |
| 5 ; RUN: | %if --need=target_X8632 --command FileCheck %s | 5 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
| 6 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ | 6 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
| 7 ; RUN: --target x8632 -i %s --args -Om1 -sandbox \ | 7 ; RUN: --target x8632 -i %s --args -Om1 -sandbox \ |
| 8 ; RUN: | %if --need=target_X8632 --command FileCheck %s | 8 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
| 9 | 9 |
| 10 ; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1 | 10 ; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1 |
| (...skipping 11 matching lines...) Expand all Loading... |
| 22 ; RUN: --target x8632 -i %s --args -O2 \ | 22 ; RUN: --target x8632 -i %s --args -O2 \ |
| 23 ; RUN: | %if --need=target_X8632 \ | 23 ; RUN: | %if --need=target_X8632 \ |
| 24 ; RUN: --command FileCheck --check-prefix=CHECKO2UNSANDBOXEDREM %s | 24 ; RUN: --command FileCheck --check-prefix=CHECKO2UNSANDBOXEDREM %s |
| 25 | 25 |
| 26 ; RUN: %if --need=target_ARM32 --need=allow_dump \ | 26 ; RUN: %if --need=target_ARM32 --need=allow_dump \ |
| 27 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ | 27 ; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \ |
| 28 ; RUN: -i %s --args -O2 --skip-unimplemented \ | 28 ; RUN: -i %s --args -O2 --skip-unimplemented \ |
| 29 ; RUN: | %if --need=target_ARM32 --need=allow_dump \ | 29 ; RUN: | %if --need=target_ARM32 --need=allow_dump \ |
| 30 ; RUN: --command FileCheck --check-prefix ARM32 %s | 30 ; RUN: --command FileCheck --check-prefix ARM32 %s |
| 31 | 31 |
| 32 | |
| 33 declare i8* @llvm.nacl.read.tp() | 32 declare i8* @llvm.nacl.read.tp() |
| 34 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) | |
| 35 declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) | |
| 36 declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1) | |
| 37 declare void @llvm.nacl.longjmp(i8*, i32) | 33 declare void @llvm.nacl.longjmp(i8*, i32) |
| 38 declare i32 @llvm.nacl.setjmp(i8*) | 34 declare i32 @llvm.nacl.setjmp(i8*) |
| 39 declare float @llvm.sqrt.f32(float) | 35 declare float @llvm.sqrt.f32(float) |
| 40 declare double @llvm.sqrt.f64(double) | 36 declare double @llvm.sqrt.f64(double) |
| 41 declare float @llvm.fabs.f32(float) | 37 declare float @llvm.fabs.f32(float) |
| 42 declare double @llvm.fabs.f64(double) | 38 declare double @llvm.fabs.f64(double) |
| 43 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) | 39 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) |
| 44 declare void @llvm.trap() | 40 declare void @llvm.trap() |
| 45 declare i16 @llvm.bswap.i16(i16) | 41 declare i16 @llvm.bswap.i16(i16) |
| 46 declare i32 @llvm.bswap.i32(i32) | 42 declare i32 @llvm.bswap.i32(i32) |
| (...skipping 53 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 100 ; Not actually using the result of nacl read tp call. | 96 ; Not actually using the result of nacl read tp call. |
| 101 ; In O2 mode this should be DCE'ed. | 97 ; In O2 mode this should be DCE'ed. |
| 102 ret i32 %a | 98 ret i32 %a |
| 103 } | 99 } |
| 104 ; Consider nacl.read.tp side-effect free, so it can be eliminated. | 100 ; Consider nacl.read.tp side-effect free, so it can be eliminated. |
| 105 ; CHECKO2REM-LABEL: test_nacl_read_tp_dead | 101 ; CHECKO2REM-LABEL: test_nacl_read_tp_dead |
| 106 ; CHECKO2REM-NOT: mov e{{.*}}, DWORD PTR gs:0x0 | 102 ; CHECKO2REM-NOT: mov e{{.*}}, DWORD PTR gs:0x0 |
| 107 ; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_dead | 103 ; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_dead |
| 108 ; CHECKO2UNSANDBOXEDREM-NOT: call {{.*}} R_{{.*}} __nacl_read_tp | 104 ; CHECKO2UNSANDBOXEDREM-NOT: call {{.*}} R_{{.*}} __nacl_read_tp |
| 109 | 105 |
| 110 define void @test_memcpy(i32 %iptr_dst, i32 %iptr_src, i32 %len) { | |
| 111 entry: | |
| 112 %dst = inttoptr i32 %iptr_dst to i8* | |
| 113 %src = inttoptr i32 %iptr_src to i8* | |
| 114 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, | |
| 115 i32 %len, i32 1, i1 false) | |
| 116 ret void | |
| 117 } | |
| 118 ; CHECK-LABEL: test_memcpy | |
| 119 ; CHECK: call {{.*}} R_{{.*}} memcpy | |
| 120 ; CHECKO2REM-LABEL: test_memcpy | |
| 121 ; CHECKO2UNSANDBOXEDREM-LABEL: test_memcpy | |
| 122 ; ARM32-LABEL: test_memcpy | |
| 123 ; ARM32: bl {{.*}} memcpy | |
| 124 | |
| 125 ; TODO(jvoung) -- if we want to be clever, we can do this and the memmove, | |
| 126 ; memset without a function call. | |
| 127 define void @test_memcpy_const_len_align(i32 %iptr_dst, i32 %iptr_src) { | |
| 128 entry: | |
| 129 %dst = inttoptr i32 %iptr_dst to i8* | |
| 130 %src = inttoptr i32 %iptr_src to i8* | |
| 131 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, | |
| 132 i32 32, i32 1, i1 false) | |
| 133 ret void | |
| 134 } | |
| 135 ; CHECK-LABEL: test_memcpy_const_len_align | |
| 136 ; CHECK: call {{.*}} R_{{.*}} memcpy | |
| 137 ; ARM32-LABEL: test_memcpy_const_len_align | |
| 138 ; ARM32: bl {{.*}} memcpy | |
| 139 | |
| 140 define void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) { | |
| 141 entry: | |
| 142 %dst = inttoptr i32 %iptr_dst to i8* | |
| 143 %src = inttoptr i32 %iptr_src to i8* | |
| 144 call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src, | |
| 145 i32 %len, i32 1, i1 false) | |
| 146 ret void | |
| 147 } | |
| 148 ; CHECK-LABEL: test_memmove | |
| 149 ; CHECK: call {{.*}} R_{{.*}} memmove | |
| 150 ; ARM32-LABEL: test_memmove | |
| 151 ; ARM32: bl {{.*}} memmove | |
| 152 | |
| 153 define void @test_memmove_const_len_align(i32 %iptr_dst, i32 %iptr_src) { | |
| 154 entry: | |
| 155 %dst = inttoptr i32 %iptr_dst to i8* | |
| 156 %src = inttoptr i32 %iptr_src to i8* | |
| 157 call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src, | |
| 158 i32 32, i32 1, i1 false) | |
| 159 ret void | |
| 160 } | |
| 161 ; CHECK-LABEL: test_memmove_const_len_align | |
| 162 ; CHECK: call {{.*}} R_{{.*}} memmove | |
| 163 ; ARM32-LABEL: test_memmove_const_len_align | |
| 164 ; ARM32: bl {{.*}} memmove | |
| 165 | |
| 166 define void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) { | |
| 167 entry: | |
| 168 %val = trunc i32 %wide_val to i8 | |
| 169 %dst = inttoptr i32 %iptr_dst to i8* | |
| 170 call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val, | |
| 171 i32 %len, i32 1, i1 false) | |
| 172 ret void | |
| 173 } | |
| 174 ; CHECK-LABEL: test_memset | |
| 175 ; CHECK: movzx | |
| 176 ; CHECK: call {{.*}} R_{{.*}} memset | |
| 177 ; ARM32-LABEL: test_memset | |
| 178 ; ARM32: uxtb | |
| 179 ; ARM32: bl {{.*}} memset | |
| 180 | |
| 181 define void @test_memset_const_len_align(i32 %iptr_dst, i32 %wide_val) { | |
| 182 entry: | |
| 183 %val = trunc i32 %wide_val to i8 | |
| 184 %dst = inttoptr i32 %iptr_dst to i8* | |
| 185 call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val, | |
| 186 i32 32, i32 1, i1 false) | |
| 187 ret void | |
| 188 } | |
| 189 ; CHECK-LABEL: test_memset_const_len_align | |
| 190 ; CHECK: movzx | |
| 191 ; CHECK: call {{.*}} R_{{.*}} memset | |
| 192 ; ARM32-LABEL: test_memset_const_len_align | |
| 193 ; ARM32: uxtb | |
| 194 ; ARM32: bl {{.*}} memset | |
| 195 | |
| 196 define void @test_memset_const_val(i32 %iptr_dst, i32 %len) { | |
| 197 entry: | |
| 198 %dst = inttoptr i32 %iptr_dst to i8* | |
| 199 call void @llvm.memset.p0i8.i32(i8* %dst, i8 0, i32 %len, i32 1, i1 false) | |
| 200 ret void | |
| 201 } | |
| 202 ; CHECK-LABEL: test_memset_const_val | |
| 203 ; Make sure the argument is legalized (can't movzx reg, 0). | |
| 204 ; CHECK: movzx {{.*}},{{[^0]}} | |
| 205 ; CHECK: call {{.*}} R_{{.*}} memset | |
| 206 ; ARM32-LABEL: test_memset_const_val | |
| 207 ; ARM32: uxtb | |
| 208 ; ARM32: bl {{.*}} memset | |
| 209 | |
| 210 define i32 @test_setjmplongjmp(i32 %iptr_env) { | 106 define i32 @test_setjmplongjmp(i32 %iptr_env) { |
| 211 entry: | 107 entry: |
| 212 %env = inttoptr i32 %iptr_env to i8* | 108 %env = inttoptr i32 %iptr_env to i8* |
| 213 %i = call i32 @llvm.nacl.setjmp(i8* %env) | 109 %i = call i32 @llvm.nacl.setjmp(i8* %env) |
| 214 %r1 = icmp eq i32 %i, 0 | 110 %r1 = icmp eq i32 %i, 0 |
| 215 br i1 %r1, label %Zero, label %NonZero | 111 br i1 %r1, label %Zero, label %NonZero |
| 216 Zero: | 112 Zero: |
| 217 ; Redundant inttoptr, to make --pnacl cast-eliding/re-insertion happy. | 113 ; Redundant inttoptr, to make --pnacl cast-eliding/re-insertion happy. |
| 218 %env2 = inttoptr i32 %iptr_env to i8* | 114 %env2 = inttoptr i32 %iptr_env to i8* |
| 219 call void @llvm.nacl.longjmp(i8* %env2, i32 1) | 115 call void @llvm.nacl.longjmp(i8* %env2, i32 1) |
| (...skipping 406 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 626 ; At least 3 copies of esp, but probably more from having to do the allocas. | 522 ; At least 3 copies of esp, but probably more from having to do the allocas. |
| 627 ; CHECK: mov {{.*}},esp | 523 ; CHECK: mov {{.*}},esp |
| 628 ; CHECK: mov {{.*}},esp | 524 ; CHECK: mov {{.*}},esp |
| 629 ; CHECK: mov {{.*}},esp | 525 ; CHECK: mov {{.*}},esp |
| 630 ; CHECK: mov esp,{{.*}} | 526 ; CHECK: mov esp,{{.*}} |
| 631 ; ARM32-LABEL: test_stacksave_multiple | 527 ; ARM32-LABEL: test_stacksave_multiple |
| 632 ; ARM32: mov {{.*}}, sp | 528 ; ARM32: mov {{.*}}, sp |
| 633 ; ARM32: mov {{.*}}, sp | 529 ; ARM32: mov {{.*}}, sp |
| 634 ; ARM32: mov {{.*}}, sp | 530 ; ARM32: mov {{.*}}, sp |
| 635 ; ARM32: mov sp, {{.*}} | 531 ; ARM32: mov sp, {{.*}} |
| OLD | NEW |