Adds a few MIPS arithmetic instructions to the simulator, assembler, disassembler

runtime/vm/assembler_mips.h

Index: runtime/vm/assembler_mips.h
===================================================================
--- runtime/vm/assembler_mips.h	(revision 19704)
+++ runtime/vm/assembler_mips.h	(working copy)
@@ -220,6 +220,62 @@
   }
 
   // CPU instructions.
+  void addi(Register rt, Register rs, const Immediate& imm) {
+    ASSERT(Utils::IsUint(16, imm.value()));

[Ivan Posva, 2013/03/11 06:03:27]

I would expect that imm is checked against Utils::IsInt(16, imm.value()) due to:
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a
32-bit result.

And then do the static cast to uint16_t below.

[zra, 2013/03/11 15:46:03]

Yah, you're right. I've already fixed this in my next CL.

+    uint16_t imm_value = static_cast<uint16_t>(imm.value());
+    EmitIType(ADDI, rs, rt, imm_value);

[Ivan Posva, 2013/03/11 06:03:27]

Also I am not sure we even use this instruction due to its trap causing
implications.

[zra, 2013/03/11 15:46:03]

Should I remove it?

+  }
+
+  void addiu(Register rt, Register rs, const Immediate& imm) {
+    ASSERT(Utils::IsUint(16, imm.value()));

[Ivan Posva, 2013/03/11 06:03:27]

ditto (sign extension)

[zra, 2013/03/11 15:46:03]

In next CL

+    uint16_t imm_value = static_cast<uint16_t>(imm.value());
+    EmitIType(ADDIU, rs, rt, imm_value);
+  }
+
+  void addu(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, ADDU);
+  }
+
+  void and_(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, AND);
+  }
+
+  void andi(Register rt, Register rs, const Immediate& imm) {
+    ASSERT(Utils::IsUint(16, imm.value()));
+    uint16_t imm_value = static_cast<uint16_t>(imm.value());
+    EmitIType(ANDI, rs, rt, imm_value);
+  }
+
+  void clo(Register rd, Register rs) {
+    EmitRType(SPECIAL2, rs, rd, rd, 0, CLO);
+  }
+
+  void clz(Register rd, Register rs) {
+    EmitRType(SPECIAL2, rs, rd, rd, 0, CLZ);
+  }
+
+  void div(Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, R0, 0, DIV);
+  }
+
+  void divu(Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
+  }
+
+  void lui(Register rt, const Immediate& imm) {
+    ASSERT(Utils::IsUint(16, imm.value()));
+    uint16_t imm_value = static_cast<uint16_t>(imm.value());
+    EmitIType(LUI, R0, rt, imm_value);
+  }
+
+  void mfhi(Register rd) {
+    EmitRType(SPECIAL, R0, R0, rd, 0, MFHI);
+  }
+
+  void mflo(Register rd) {
+    EmitRType(SPECIAL, R0, R0, rd, 0, MFLO);
+  }
+
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
@@ -233,6 +289,16 @@
     delay_slot_available_ = true;
   }
 
+  void sll(Register rd, Register rt, int sa) {
+    EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
+  }
+
+  // Macros.
+  void LoadImmediate(Register rd, int32_t value) {
+    lui(rd, Immediate((value >> 16) & 0xffff));
+    ori(rd, rd, Immediate(value & 0xffff));
+  }
+
  private:
   AssemblerBuffer buffer_;
   GrowableObjectArray& object_pool_;  // Objects and patchable jump targets.
@@ -278,6 +344,16 @@
          imm);
   }
 
+  void EmitRegImmType(Opcode opcode,
+                      Register rs,
+                      RtRegImm code,
+                      uint16_t imm) {
+    Emit(opcode << kOpcodeShift |
+         rs << kRsShift |
+         code << kRtShift |
+         imm);
+  }
+
   void EmitJType(Opcode opcode, Label* label) {
     UNIMPLEMENTED();
   }