Adds a few MIPS arithmetic instructions to the simulator, assembler, disassembler

runtime/vm/disassembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_MIPS.
 #if defined(TARGET_ARCH_MIPS)
 #include "platform/assert.h"
 
@@ skipping 18 matching lines @@
   void Print(const char* str);
 
   // Printing of common values.
   void PrintRegister(Register reg);
 
   int FormatRegister(Instr* instr, const char* format);
   int FormatOption(Instr* instr, const char* format);
   void Format(Instr* instr, const char* format);
 
   void DecodeSpecial(Instr* instr);
+  void DecodeSpecial2(Instr* instr);
 
   // Convenience functions.
   char* get_buffer() const { return buffer_; }
   char* current_position_in_buffer() { return buffer_ + buffer_pos_; }
   size_t remaining_size_in_buffer() { return buffer_size_ - buffer_pos_; }
 
   char* buffer_;  // Decode instructions into this buffer.
   size_t buffer_size_;  // The size of the character buffer.
   size_t buffer_pos_;  // Current character position in buffer.
 
@@ skipping 120 matching lines @@
       buffer_[buffer_pos_++] = cur;
     }
     cur = *format++;
   }
   buffer_[buffer_pos_]  = '\0';
 }
 
 
 void MIPSDecoder::DecodeSpecial(Instr* instr) {
   switch (instr->FunctionField()) {
+    case ADDU: {
+      Format(instr, "addu 'rd, 'rs, 'rt");
+      break;
+    }
+    case AND: {
+      Format(instr, "and 'rd, 'rs, 'rt");
+      break;
+    }
+    case DIV: {
+      Format(instr, "div 'rs, 'rt");
+      break;
+    }
+    case DIVU: {
+      Format(instr, "divu 'rs, 'rt");
+      break;
+    }
+    case MFHI: {
+      Format(instr, "mfhi 'rd");
+      break;
+    }
+    case MFLO: {
+      Format(instr, "mflo 'rd");
+      break;
+    }
     case SLL: {
       if ((instr->RdField() == R0) &&
           (instr->RtField() == R0) &&
           (instr->SaField() == 0)) {
         Format(instr, "nop");
       } else {
         Format(instr, "sll 'rd, 'rt, 'sa");
       }
       break;
     }
     case JR: {
       ASSERT(instr->RtField() == R0);
       ASSERT(instr->RdField() == R0);
       Format(instr, "jr'hint 'rs");
       break;
     }
     default: {
       OS::PrintErr("DecodeSpecial: 0x%x\n", instr->InstructionBits());
       UNREACHABLE();
       break;
     }
   }
 }
 
 
+void MIPSDecoder::DecodeSpecial2(Instr* instr) {
+  switch (instr->FunctionField()) {
+    case CLO: {
+      Format(instr, "clo 'rd, 'rs");
+    }
+    case CLZ: {
+      Format(instr, "clz 'rd, 'rs");
+    }
+    default: {
+      OS::PrintErr("DecodeSpecial2: 0x%x\n", instr->InstructionBits());
+      UNREACHABLE();
+      break;
+    }
+  }
+}
+
+
 void MIPSDecoder::InstructionDecode(Instr* instr) {
   switch (instr->OpcodeField()) {
     case SPECIAL: {
       DecodeSpecial(instr);
       break;
     }
+    case SPECIAL2: {
+      DecodeSpecial2(instr);
+      break;
+    }
+    case ADDI: {
+      Format(instr, "addi 'rt, 'rs, 'immu");
+      break;
+    }
+    case ADDIU: {
+      Format(instr, "addiu 'rt, 'rs, 'immu");
+      break;
+    }
+    case ANDI: {
+      Format(instr, "andi 'rt, 'rs, 'immu");
+      break;
+    }
     case ORI: {
       Format(instr, "ori 'rt, 'rs, 'immu");
       break;
     }
     default: {
       OS::PrintErr("Undecoded instruction: 0x%x\n", instr->InstructionBits());
       UNREACHABLE();
       break;
     }
   }
@@ skipping 39 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS