- Add a skeleton MIPS assembler, disassembler and simulator.

runtime/vm/constants_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_MIPS_H_
 #define VM_CONSTANTS_MIPS_H_
 
 namespace dart {
 
 enum Register {
-  ZR =  0,
-  AT =  1,
+  R0  =  0,
+  R1  =  1,
   kFirstFreeCpuRegister = 2,
-  V0 =  2,
-  V1 =  3,
-  A0 =  4,
-  A1 =  5,
-  A2 =  6,
-  A3 =  7,
-  T0 =  8,
-  T1 =  9,
-  T2 = 10,
-  T3 = 11,
-  T4 = 12,
-  T5 = 13,
-  T6 = 14,
-  T7 = 15,
-  S0 = 16,
-  S1 = 17,
-  S2 = 18,
-  S3 = 19,
-  S4 = 20,
-  S5 = 21,
-  S6 = 22,
-  S7 = 23,
-  T8 = 24,
-  T9 = 25,
+  R2  =  2,
+  R3  =  3,
+  R4  =  4,
+  R5  =  5,
+  R6  =  6,
+  R7  =  7,
+  R8  =  8,
+  R9  =  9,
+  R10 = 10,
+  R11 = 11,
+  R12 = 12,
+  R13 = 13,
+  R14 = 14,
+  R15 = 15,
+  R16 = 16,
+  R17 = 17,
+  R18 = 18,
+  R19 = 19,
+  R20 = 20,
+  R21 = 21,
+  R22 = 22,
+  R23 = 23,
+  R24 = 24,
+  R25 = 25,
   kLastFreeCpuRegister = 25,
-  K0 = 26,
-  K1 = 27,
-  GP = 28,
-  SP = 29,
-  FP = 30,
-  RA = 31,
+  R26 = 26,
+  R27 = 27,
+  R28 = 28,
+  R29 = 29,
+  R30 = 30,
+  R31 = 31,
   kNumberOfCpuRegisters = 32,
   kNoRegister = -1,
+
+  // Register aliases.
+  ZR = R0,
+  AT = R1,
+  V0 = R2,
+  V1 = R3,
+  A0 = R4,
+  A1 = R5,
+  A2 = R6,
+  A3 = R7,
+  T0 = R8,
+  T1 = R9,
+  T2 = R10,
+  T3 = R11,
+  T4 = R12,
+  T5 = R13,
+  T6 = R14,
+  T7 = R15,
+  S0 = R16,
+  S1 = R17,
+  S3 = R18,
+  S4 = R19,
+  S5 = R20,
+  S6 = R21,
+  S7 = R22,
+  T8 = R24,
+  T9 = R25,
+  K0 = R26,
+  K1 = R27,
+  GP = R28,
+  SP = R29,
+  FP = R30,
+  RA = R31,
 };
 
 
 // Values for double-precision floating point registers.
 enum FRegister {
   F0  =  0,
   F1  =  1,
   F2  =  2,
   F3  =  3,
   F4  =  4,
@@ skipping 42 matching lines @@
 const Register SPREG = SP;  // Stack pointer register.
 const Register FPREG = FP;  // Frame pointer register.
 
 
 // Values for the condition field.  // UNIMPLEMENTED.
 enum Condition {
   kNoCondition = -1,
   kMaxCondition = 16,
 };
 
+
+// Constants used for the decoding or encoding of the individual fields of
+// instructions. Based on the "Table 4.25 CPU Instruction Format Fields".
+enum InstructionFields {
+  kOpcodeShift = 26,
+  kOpcodeBits = 6,
+  kRsShift = 21,
+  kRsBits = 5,
+  kRtShift = 16,
+  kRtBits = 5,
+  kRdShift = 11,
+  kRdBits = 5,
+  kSaShift = 6,
+  kSaBits = 5,
+  kFunctionShift = 0,
+  kFunctionBits = 6,
+  kImmShift = 0,
+  kImmBits = 16,
+  kInstrShift = 0,
+  kInstrBits = 26,
+};
+
+
+enum Opcode {
+  SPECIAL = 0,
+  REGIMM = 1,
+  J = 2,
+  JAL = 3,
+  BEQ = 4,
+  BNE = 5,
+  BLEZ = 6,
+  BGTZ = 7,
+  ADDI = 8,
+  ADDIU = 9,
+  SLTI = 10,
+  SLTIU = 11,
+  ANDI = 12,
+  ORI = 13,
+  XORI = 14,
+  LUI = 15,
+  CPO0 = 16,
+  COP1 = 17,
+  COP2 = 18,
+  COP1X = 19,
+  BEQL = 20,
+  BNEL = 21,
+  BLEZL = 22,
+  BGTZL = 23,
+  SPECIAL2 = 28,
+  JALX = 29,
+  SPECIAL3 = 31,
+  LB = 32,
+  LH = 33,
+  LWL = 34,
+  LW = 35,
+  LBU = 36,
+  LHU = 37,
+  LWR = 38,
+  SB = 40,
+  SH = 41,
+  SWL = 42,
+  SW = 43,
+  SWR = 46,
+  CACHE = 47,
+  LL = 48,
+  LWC1 = 49,
+  LWC2 = 50,
+  PREF = 51,
+  LDC1 = 53,
+  LDC2 = 54,
+  SC = 56,
+  SWC1 = 57,
+  SWC2 = 58,
+  SDC1 = 61,
+  SDC2 = 62,
+};
+
+
+enum SpecialFunction {
+  SLL = 0,
+  MOVCI = 1,
+  SRL = 2,
+  SRA = 3,
+  SLLV = 4,
+  SRLV = 6,
+  SRAV = 7,
+  JR = 8,
+  JALR = 9,
+  MOVZ = 10,
+  MOVN = 11,
+  SYSCALL = 12,
+  BREAK = 13,
+  SYNC = 15,
+  MFHI,

[regis, 2013/03/06 21:18:42]

= 16
etc...

[Ivan Posva, 2013/03/07 11:03:22]

Done. I wasn't sure which one is more readable. I guess it is better to not
leave any questions.

[regis, 2013/03/07 17:56:57]

It looks like you forgot to upload before committing.

+  MTHI,
+  MFLO,
+  MTLO,
+  MULT = 24,
+  MUTLU,
+  DIV,
+  DIVU,
+  ADD = 32,
+  ADDU,
+  SUB,
+  SUBU,
+  AND,
+  OR,
+  XOR,
+  NOR,
+  SLT = 42,
+  SLTU,
+  TGE = 48,
+  TGEU,
+  TLT,
+  TLTU,
+  TEQ,
+  TNE = 54,
+};
+
+
+enum RtRegImm {
+  BLTZ = 0,
+  BGEZ,

[regis, 2013/03/06 21:18:42]

fill in enum values

[Ivan Posva, 2013/03/07 11:03:22]

Done.

+  BLTZL,
+  BGEZL,
+  TGEI = 8,
+  TGEIU,
+  TLTI,
+  TLTIU,
+  TEQI,
+  TNEI = 14,
+  BLTZAL = 16,
+  BGEZAL,
+  BLTZALL,
+  BGEZALL,
+  SYNCI = 31,
+};
+
+
+class Instr {
+ public:
+  enum {
+    kInstrSize = 4,
+  };
+
+  static const int32_t kBreakPointInstruction =
+      (SPECIAL << kOpcodeShift) | (BREAK << kFunctionShift);
+
+  // Get the raw instruction bits.
+  inline int32_t InstructionBits() const {
+    return reinterpret_cast<int32_t>(this);
+  }
+
+  // Read one particular bit out of the instruction bits.
+  inline int Bit(int nr) const {
+    return (InstructionBits() >> nr) & 1;
+  }
+
+  // Read a bit field out of the instruction bits.
+  inline int Bits(int shift, int count) const {
+    return (InstructionBits() >> shift) & ((1 << count) - 1);
+  }
+
+  // Accessors to the different named fields used in the MIPS encoding.
+  inline Opcode OpcodeField() const {
+    return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
+  }
+
+  inline Register RsField() const {
+    return static_cast<Register>(Bits(kRsShift, kRsBits));
+  }
+
+  inline Register RtField() const {
+    return static_cast<Register>(Bits(kRtShift, kRtBits));
+  }
+
+  inline Register RdField() const {
+    return static_cast<Register>(Bits(kRdShift, kRdBits));
+  }
+
+  inline int SaField() const {
+    return Bits(kSaShift, kSaBits);
+  }
+
+  inline int32_t ImmField() const {
+    return static_cast<int32_t>(Bits(kImmShift, kImmBits));
+  }
+
+  inline SpecialFunction FunctionField() const {
+    return static_cast<SpecialFunction>(Bits(kFunctionShift, kFunctionBits));
+  }
+
+  // Instructions are read out of a code stream. The only way to get a
+  // reference to an instruction is to convert a pc. There is no way
+  // to allocate or create instances of class Instr.
+  // Use the At(pc) function to create references to Instr.
+  static Instr* At(uword pc) {
+    return reinterpret_cast<Instr*>(*reinterpret_cast<int32_t*>(pc));
+  }
+
+ private:
+  DISALLOW_ALLOCATION();
+  DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
+};
+
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_MIPS_H_