- Add a skeleton MIPS assembler, disassembler and simulator.

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
 
 #include "platform/assert.h"
 #include "vm/constants_mips.h"
 
 namespace dart {
 
-class Operand : public ValueObject {
+class Immediate : public ValueObject {
  public:
-  Operand(const Operand& other) : ValueObject() {
+  explicit Immediate(int32_t value) : value_(value) { }
+
+  Immediate(const Immediate& other) : ValueObject(), value_(other.value_) { }
+  Immediate& operator=(const Immediate& other) {
+    value_ = other.value_;
+    return *this;
+  }
+
+ private:
+  int32_t value_;
+
+  int32_t value() const { return value_; }
+
+  friend class Assembler;
+};
+
+
+class Address : public ValueObject {
+ public:
+  Address(Register base, int32_t offset) {
     UNIMPLEMENTED();
   }
 
-  Operand& operator=(const Operand& other) {
-    UNIMPLEMENTED();
+  Address(const Address& other)
+      : ValueObject(), base_(other.base_), offset_(other.offset_) { }
+  Address& operator=(const Address& other) {
+    base_ = other.base_;
+    offset_ = other.offset_;
     return *this;
   }
 
- protected:
-  Operand() { }  // Needed by subclass Address.
+ private:
+  Register base_;
+  int32_t offset_;
 };
 
 
-class Address : public Operand {
- public:
-  Address(Register base, int32_t disp) {
-    UNIMPLEMENTED();
-  }
-
-  Address(const Address& other) : Operand(other) { }
-
-  Address& operator=(const Address& other) {
-    Operand::operator=(other);
-    return *this;
-  }
-};
-
-
 class FieldAddress : public Address {
  public:
   FieldAddress(Register base, int32_t disp)
       : Address(base, disp - kHeapObjectTag) { }
 
   FieldAddress(const FieldAddress& other) : Address(other) { }
 
   FieldAddress& operator=(const FieldAddress& other) {
     Address::operator=(other);
     return *this;
@@ skipping 66 matching lines @@
 
   void PopRegister(Register r) {
     UNIMPLEMENTED();
   }
 
   void Bind(Label* label) {
     UNIMPLEMENTED();
   }
 
   // Misc. functionality
-  int CodeSize() const {
-    UNIMPLEMENTED();
-    return 0;
+  int CodeSize() const { return buffer_.Size(); }
+  int prologue_offset() const { return -1; }
+  const ZoneGrowableArray<int>& GetPointerOffsets() const {
+    return buffer_.pointer_offsets();
   }
-  int prologue_offset() const {
-    UNIMPLEMENTED();
-    return 0;
-  }
-  const ZoneGrowableArray<int>& GetPointerOffsets() const {
-    UNIMPLEMENTED();
-    return *pointer_offsets_;
-  }
-  const GrowableObjectArray& object_pool() const {
-    UNIMPLEMENTED();
-    return object_pool_;
-  }
+  const GrowableObjectArray& object_pool() const { return object_pool_; }
   void FinalizeInstructions(const MemoryRegion& region) {
-    UNIMPLEMENTED();
+    buffer_.FinalizeInstructions(region);
   }
 
   // Set up a Dart frame on entry with a frame pointer and PC information to
   // enable easy access to the RawInstruction object of code corresponding
   // to this frame.
   void EnterDartFrame(intptr_t frame_size) {
     UNIMPLEMENTED();
   }
 
   // Set up a stub frame so that the stack traversal code can easily identify
@@ skipping 17 matching lines @@
                    Register instance_reg) {
     UNIMPLEMENTED();
   }
 
   // Debugging and bringup support.
   void Stop(const char* message) { UNIMPLEMENTED(); }
   void Unimplemented(const char* message);
   void Untested(const char* message);
   void Unreachable(const char* message);
 
-  static void InitializeMemoryWithBreakpoints(uword data, int length) {
-    UNIMPLEMENTED();
-  }
+  static void InitializeMemoryWithBreakpoints(uword data, int length);
 
   void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
 
   const Code::Comments& GetCodeComments() const;
 
   static const char* RegisterName(Register reg) {
     UNIMPLEMENTED();
     return NULL;
   }
 
   static const char* FpuRegisterName(FpuRegister reg) {
     UNIMPLEMENTED();
     return NULL;
   }
 
+  // CPU instructions.
+  void ori(Register rt, Register rs, const Immediate& imm) {

[regis, 2013/03/06 21:18:42]

Are we accepting negative immediate values? See comments in EmitIType below.

[Ivan Posva, 2013/03/07 11:03:22]

I fixed the imm parameter of EmitIType to be uint16_t. As you point out the
checking for the correct size needs to be done here. For ori it needs to be
Utils::Uint(16, value), while for others the isntruction set has other
requirements.

+    EmitIType(ORI, rs, rt, imm);

[regis, 2013/03/06 21:18:42]

The body should be moved to the cc file. Ditto for other functions below.

[Ivan Posva, 2013/03/07 11:03:22]

There is no reason to prevent inlining this function.

+  }
+
+  void jr(Register rs) {

[regis, 2013/03/06 21:18:42]

This should be Jr, with a capital letter, because it generates more than one
instruction. Alternatively, the NOP should not be emitted as part of jr, but as
part of a Ret() macro instruction.

[Ivan Posva, 2013/03/07 11:03:22]

As discussed offline the only sane way to look at jr in light of branch delays
is to consider it being a two-word wide instruction.

+    EmitRType(SPECIAL, rs, R0, R0, Immediate(0), JR);
+    Emit(0);  // Branch delay NOP.
+  }
+
  private:
   AssemblerBuffer buffer_;
   GrowableObjectArray& object_pool_;  // Objects and patchable jump targets.
-  ZoneGrowableArray<int>* pointer_offsets_;
   int prologue_offset_;
 
   class CodeComment : public ZoneAllocated {
    public:
     CodeComment(intptr_t pc_offset, const String& comment)
         : pc_offset_(pc_offset), comment_(comment) { }
 
     intptr_t pc_offset() const { return pc_offset_; }
     const String& comment() const { return comment_; }
 
    private:
     intptr_t pc_offset_;
     const String& comment_;
 
     DISALLOW_COPY_AND_ASSIGN(CodeComment);
   };
 
   GrowableArray<CodeComment*> comments_;
 
+  void Emit(int32_t value) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    buffer_.Emit<int32_t>(value);
+  }
+
+  // Encode CPU instructions according to the types specified in
+  // Figures 4-1, 4-2 and 4-3.

[regis, 2013/03/06 21:18:42]

What figures are you referring to?

[Ivan Posva, 2013/03/07 11:03:22]

Done.

[regis, 2013/03/07 17:56:57]

Done what?

+  void EmitIType(Opcode opcode,
+                 Register rs,
+                 Register rt,
+                 const Immediate& imm) {
+    int32_t imm_value = imm.value();
+    ASSERT(Utils::IsInt(16, imm_value));

[regis, 2013/03/06 21:18:42]

I am not sure this is correct. It depends on what the instruction is passing in
as imm value. I suppose that EmitIType will be used for both sign-extended
values and zero-extended values. Passing -1 as the immediate value would
silently generate a bad instruction without the missing mask below.

[Ivan Posva, 2013/03/07 11:03:22]

Fixed. EmitIType expects a uint16_t imm now.

+    Emit(opcode << kOpcodeShift |
+         rs << kRsShift |
+         rt << kRtShift |
+         imm_value);

[regis, 2013/03/06 21:18:42]

imm_value & 0xffff

+  }
+
+  void EmitJType(Opcode opcode, Label* label) {
+    UNIMPLEMENTED();
+  }
+
+  void EmitRType(Opcode opcode,
+                 Register rs,
+                 Register rt,
+                 Register rd,
+                 Immediate sa,
+                 SpecialFunction func) {
+    int32_t sa_value = sa.value();
+    ASSERT(Utils::IsInt(5, sa_value));

[regis, 2013/03/06 21:18:42]

IsUint()?

[Ivan Posva, 2013/03/07 11:03:22]

Done.

+    Emit(opcode << kOpcodeShift |
+         rs << kRsShift |
+         rt << kRtShift |
+         rd << kRdShift |
+         sa_value << kSaShift |

[regis, 2013/03/06 21:18:42]

(sa_value & 0x1f) << kSaShift

[Ivan Posva, 2013/03/07 11:03:22]

Similar fix to EmitIType. We now pass sa as a uint8_t and assert that only 5
bits are used.

+         func << kFunctionShift);
+  }
+
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_