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Unified Diff: src/IceTargetLoweringMIPS32.cpp

Issue 1253833002: Subzero: Cleanly implement register allocation after phi lowering. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Improve translation-time performance Created 5 years, 5 months ago
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Index: src/IceTargetLoweringMIPS32.cpp
diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp
index add97b36dd8abcae2d278ed6e015442ee380b2d1..99c992827475a222248838f4f07d062e42dd367f 100644
--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -648,15 +648,6 @@ void TargetMIPS32::prelowerPhis() {
UnimplementedError(Func->getContext()->getFlags());
}
-// Lower the pre-ordered list of assignments into mov instructions.
-// Also has to do some ad-hoc register allocation as necessary.
-void TargetMIPS32::lowerPhiAssignments(CfgNode *Node,
- const AssignList &Assignments) {
- (void)Node;
- (void)Assignments;
- UnimplementedError(Func->getContext()->getFlags());
-}
-
void TargetMIPS32::postLower() {
if (Ctx->getFlags().getOptLevel() == Opt_m1)
return;
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