Subzero: Cleanly implement register allocation after phi lowering.

src/IceClFlags.cpp

Index: src/IceClFlags.cpp
diff --git a/src/IceClFlags.cpp b/src/IceClFlags.cpp
index c6ea696832add1cc872e7f80ed00af082ec60cba..cbacd8bfad540facb3dfb4b97631960a84c1a915 100644
--- a/src/IceClFlags.cpp
+++ b/src/IceClFlags.cpp
@@ -401,15 +401,7 @@ void ClFlags::getParsedClFlags(ClFlags &OutFlags) {
   OutFlags.setFunctionSections(::FunctionSections);
   OutFlags.setNumTranslationThreads(::NumThreads);
   OutFlags.setOptLevel(::OLevel);
-  if (::TargetArch == Target_ARM32) {
-    // TODO(jvoung): We need lowerPhiAssignments to handle spilling
-    // more than one register, since some ARM lowerAssign sequences
-    // may require more than one register. For now, disable PhiEdgeSplit
-    // to avoid requiring lowerPhiAssignments.
-    OutFlags.setPhiEdgeSplit(false);
-  } else {
-    OutFlags.setPhiEdgeSplit(::EnablePhiEdgeSplit);
-  }
+  OutFlags.setPhiEdgeSplit(::EnablePhiEdgeSplit);
   OutFlags.setRandomSeed(::RandomSeed);
   OutFlags.setShouldDoNopInsertion(::ShouldDoNopInsertion);
   OutFlags.setShouldRandomizeRegAlloc(::RandomizeRegisterAllocation);