Subzero: Cleanly implement register allocation after phi lowering.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 193 matching lines @@
       break;
     }
 
     postLower();
   }
 
   Context.advanceCur();
   Context.advanceNext();
 }
 
+void TargetLowering::lowerInst(CfgNode *Node, InstList::iterator Next,
+                               InstHighLevel *Instr) {
+  // TODO(stichnot): Consider modifying the design/implementation to avoid
+  // multiple init() calls when using lowerInst() to lower several instructions
+  // in the same node.
+  Context.init(Node);
+  Context.setNext(Next);
+  Context.insert(Instr);
+  --Next;
+  assert(&*Next == Instr);
+  Context.setCur(Next);
+  lower();
+}
+
 void TargetLowering::lowerOther(const Inst *Instr) {
   (void)Instr;
   Func->setError("Can't lower unsupported instruction type");
 }
 
 // Drives register allocation, allowing all physical registers (except
 // perhaps for the frame pointer) to be allocated.  This set of
 // registers could potentially be parameterized if we want to restrict
 // registers e.g. for performance testing.
 void TargetLowering::regAlloc(RegAllocKind Kind) {
@@ skipping 341 matching lines @@
   if (Target == Target_##X)                                                    \
     return TargetHeader##X::create(Ctx);
 #include "llvm/Config/SZTargets.def"
 
   llvm::report_fatal_error("Unsupported target header lowering");
 }
 
 TargetHeaderLowering::~TargetHeaderLowering() = default;
 
 } // end of namespace Ice