Subzero: Cleanly implement register allocation after phi lowering.

src/IceTargetLoweringMIPS32.cpp

 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 630 matching lines @@
 }
 
 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to
 // preserve integrity of liveness analysis.  Undef values are also
 // turned into zeroes, since loOperand() and hiOperand() don't expect
 // Undef input.
 void TargetMIPS32::prelowerPhis() {
   UnimplementedError(Func->getContext()->getFlags());
 }
 
-// Lower the pre-ordered list of assignments into mov instructions.
-// Also has to do some ad-hoc register allocation as necessary.
-void TargetMIPS32::lowerPhiAssignments(CfgNode *Node,
-                                       const AssignList &Assignments) {
-  (void)Node;
-  (void)Assignments;
-  UnimplementedError(Func->getContext()->getFlags());
-}
-
 void TargetMIPS32::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   // Find two-address non-SSA instructions where Dest==Src0, and set
   // the DestNonKillable flag to keep liveness analysis consistent.
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetMIPS32::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<int32_t> &Permutation,
@@ skipping 39 matching lines @@
 void TargetDataMIPS32::lowerConstants() {
   if (Ctx->getFlags().getDisableTranslation())
     return;
   UnimplementedError(Ctx->getFlags());
 }
 
 TargetHeaderMIPS32::TargetHeaderMIPS32(GlobalContext *Ctx)
     : TargetHeaderLowering(Ctx) {}
 
 } // end of namespace Ice