Subzero: Cleanly implement register allocation after phi lowering.

src/IceTargetLowering.h

 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 45 matching lines @@
   }
   CfgNode *getNode() const { return Node; }
   bool atEnd() const { return Cur == End; }
   InstList::iterator getCur() const { return Cur; }
   InstList::iterator getNext() const { return Next; }
   InstList::iterator getEnd() const { return End; }
   void insert(Inst *Inst);
   Inst *getLastInserted() const;
   void advanceCur() { Cur = Next; }
   void advanceNext() { advanceForward(Next); }
+  void setCur(InstList::iterator C) { Cur = C; }
+  void setNext(InstList::iterator N) { Next = N; }
   void rewind();
   void setInsertPoint(const InstList::iterator &Position) { Next = Position; }
 
 private:
   /// Node is the argument to Inst::updateVars().
   CfgNode *Node = nullptr;
   Inst *LastInserted = nullptr;
   /// Cur points to the current instruction being considered.  It is
   /// guaranteed to point to a non-deleted instruction, or to be End.
   InstList::iterator Cur;
@@ skipping 53 matching lines @@
   virtual void translateO2() {
     Func->setError("Target doesn't specify O2 lowering steps.");
   }
 
   /// Tries to do address mode optimization on a single instruction.
   void doAddressOpt();
   /// Randomly insert NOPs.
   void doNopInsertion();
   /// Lowers a single non-Phi instruction.
   void lower();
+  /// Inserts and lowers a single high-level instruction at a specific insertion
+  /// point.
+  void lowerInst(CfgNode *Node, InstList::iterator Next, InstHighLevel *Instr);
   /// Does preliminary lowering of the set of Phi instructions in the
   /// current node.  The main intention is to do what's needed to keep
   /// the unlowered Phi instructions consistent with the lowered
   /// non-Phi instructions, e.g. to lower 64-bit operands on a 32-bit
   /// target.
   virtual void prelowerPhis() {}
-  /// Lowers a list of "parallel" assignment instructions representing
-  /// a topological sort of the Phi instructions.
-  virtual void lowerPhiAssignments(CfgNode *Node,
-                                   const AssignList &Assignments) = 0;
   /// Tries to do branch optimization on a single instruction.  Returns
   /// true if some optimization was done.
   virtual bool doBranchOpt(Inst * /*I*/, const CfgNode * /*NextNode*/) {
     return false;
   }
 
   virtual SizeT getNumRegisters() const = 0;
   /// Returns a variable pre-colored to the specified physical
   /// register.  This is generally used to get very direct access to
   /// the register such as in the prolog or epilog or for marking
@@ skipping 267 matching lines @@
   virtual void lower() {}
 
 protected:
   explicit TargetHeaderLowering(GlobalContext *Ctx) : Ctx(Ctx) {}
   GlobalContext *Ctx;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERING_H