Adds MIPS instructions to simulator, assembler, disassembler

runtime/vm/assembler_mips.h

Index: runtime/vm/assembler_mips.h
===================================================================
--- runtime/vm/assembler_mips.h	(revision 19730)
+++ runtime/vm/assembler_mips.h	(working copy)
@@ -41,9 +41,8 @@
 
 class Address : public ValueObject {
  public:
-  Address(Register base, int32_t offset) {
-    UNIMPLEMENTED();
-  }
+  Address(Register base, int32_t offset = 0)
+      : ValueObject(), base_(base), offset_(offset) { }
 
   Address(const Address& other)
       : ValueObject(), base_(other.base_), offset_(other.offset_) { }
@@ -53,6 +52,12 @@
     return *this;
   }
 
+  uint32_t encoding() const {
+    ASSERT(Utils::IsInt(16, offset_));
+    uint16_t imm_value = static_cast<uint16_t>(offset_);
+    return (base_ << kRsShift) | imm_value;
+  }
+
  private:
   Register base_;
   int32_t offset_;
@@ -220,14 +225,8 @@
   }
 
   // CPU instructions.
-  void addi(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
-    uint16_t imm_value = static_cast<uint16_t>(imm.value());
-    EmitIType(ADDI, rs, rt, imm_value);
-  }
-
   void addiu(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsInt(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDIU, rs, rt, imm_value);
   }
@@ -262,12 +261,33 @@
     EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
   }
 
+
+  void lb(Register rt, const Address& addr) {
+    EmitLoadStore(LB, rt, addr);
+  }
+
+  void lbu(Register rt, const Address& addr) {
+    EmitLoadStore(LBU, rt, addr);
+  }
+
+  void lh(Register rt, const Address& addr) {
+    EmitLoadStore(LH, rt, addr);
+  }
+
+  void lhu(Register rt, const Address& addr) {
+    EmitLoadStore(LHU, rt, addr);
+  }
+
   void lui(Register rt, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(LUI, R0, rt, imm_value);
   }
 
+  void lw(Register rt, const Address& addr) {
+    EmitLoadStore(LW, rt, addr);
+  }
+
   void mfhi(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFHI);
   }
@@ -289,6 +309,18 @@
     delay_slot_available_ = true;
   }
 
+  void sb(Register rt, const Address& addr) {
+    EmitLoadStore(SB, rt, addr);
+  }
+
+  void sh(Register rt, const Address& addr) {
+    EmitLoadStore(SH, rt, addr);
+  }
+
+  void sw(Register rt, const Address& addr) {
+    EmitLoadStore(SW, rt, addr);
+  }
+
   void sll(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
   }
@@ -344,6 +376,13 @@
          imm);
   }
 
+  void EmitLoadStore(Opcode opcode, Register rt,
+                     const Address &addr) {
+    Emit(opcode << kOpcodeShift |
+         rt << kRtShift |
+         addr.encoding());
+  }
+
   void EmitRegImmType(Opcode opcode,
                       Register rs,
                       RtRegImm code,