Adds MIPS instructions to simulator, assembler, disassembler

runtime/vm/disassembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_MIPS.
 #if defined(TARGET_ARCH_MIPS)
 #include "platform/assert.h"
 
@@ skipping 19 matching lines @@
 
   // Printing of common values.
   void PrintRegister(Register reg);
 
   int FormatRegister(Instr* instr, const char* format);
   int FormatOption(Instr* instr, const char* format);
   void Format(Instr* instr, const char* format);
 
   void DecodeSpecial(Instr* instr);
   void DecodeSpecial2(Instr* instr);
+  void DecodeSpecial3(Instr* instr);
 
   // Convenience functions.
   char* get_buffer() const { return buffer_; }
   char* current_position_in_buffer() { return buffer_ + buffer_pos_; }
   size_t remaining_size_in_buffer() { return buffer_size_ - buffer_pos_; }
 
   char* buffer_;  // Decode instructions into this buffer.
   size_t buffer_size_;  // The size of the character buffer.
   size_t buffer_pos_;  // Current character position in buffer.
 
@@ skipping 119 matching lines @@
     } else {
       buffer_[buffer_pos_++] = cur;
     }
     cur = *format++;
   }
   buffer_[buffer_pos_]  = '\0';
 }
 
 
 void MIPSDecoder::DecodeSpecial(Instr* instr) {
+  ASSERT(instr->OpcodeField() == SPECIAL);
   switch (instr->FunctionField()) {
     case ADDU: {
       Format(instr, "addu 'rd, 'rs, 'rt");
       break;
     }
     case AND: {
       Format(instr, "and 'rd, 'rs, 'rt");
       break;
     }
     case DIV: {
@@ skipping 31 matching lines @@
     default: {
       OS::PrintErr("DecodeSpecial: 0x%x\n", instr->InstructionBits());
       UNREACHABLE();
       break;
     }
   }
 }
 
 
 void MIPSDecoder::DecodeSpecial2(Instr* instr) {
+  ASSERT(instr->OpcodeField() == SPECIAL2);
   switch (instr->FunctionField()) {
     case CLO: {
       Format(instr, "clo 'rd, 'rs");
       break;
     }
     case CLZ: {
       Format(instr, "clz 'rd, 'rs");
       break;
     }
     default: {
       OS::PrintErr("DecodeSpecial2: 0x%x\n", instr->InstructionBits());
       UNREACHABLE();
       break;
     }
   }
 }
 
 
+void MIPSDecoder::DecodeSpecial3(Instr* instr) {
+  ASSERT(instr->OpcodeField() == SPECIAL3);
+  switch (instr->FunctionField()) {
+    case EXT: {
+      Format(instr, "ext 'rt, 'rs, 'sa, 'rd");

[Ivan Posva, 2013/03/11 17:29:04]

'rd is certainly incorrect here. It will print the register and not the size.
Additionally you need to do some math on the values to map them back to pos and
size from their encoding. I suggest you create a new format option for this,
such as 'pos.

+      break;
+    }
+    case INS: {
+      Format(instr, "ins 'rt, 'rs, 'sa, 'rd");

[Ivan Posva, 2013/03/11 17:29:04]

ditto

+      break;
+    }
+    default: {
+      OS::PrintErr("DecodeSpecial3: 0x%x\n", instr->InstructionBits());
+      UNREACHABLE();
+      break;
+    }
+  }
+}
+
+
 void MIPSDecoder::InstructionDecode(Instr* instr) {
   switch (instr->OpcodeField()) {
     case SPECIAL: {
       DecodeSpecial(instr);
       break;
     }
     case SPECIAL2: {
       DecodeSpecial2(instr);
       break;
     }
+    case SPECIAL3: {
+      DecodeSpecial3(instr);
+      break;
+    }
     case ADDI: {
-      Format(instr, "addi 'rt, 'rs, 'immu");
+      Format(instr, "addi 'rt, 'rs, 'imms");
       break;
     }
     case ADDIU: {
-      Format(instr, "addiu 'rt, 'rs, 'immu");
+      Format(instr, "addiu 'rt, 'rs, 'imms");
       break;
     }
     case ANDI: {
       Format(instr, "andi 'rt, 'rs, 'immu");
       break;
     }
+    case LB: {
+      Format(instr, "lb 'rt, 'imms('rs)");
+      break;
+    }
+    case LBU: {
+      Format(instr, "lbu 'rt, 'imms('rs)");
+      break;
+    }
+    case LH: {
+      Format(instr, "lh 'rt, 'imms('rs)");
+      break;
+    }
     case LUI: {
       Format(instr, "lui 'rt, 'immu");
       break;
     }
+    case LW: {
+      Format(instr, "lw 'rt, 'imms('rs)");
+      break;
+    }
     case ORI: {
       Format(instr, "ori 'rt, 'rs, 'immu");
       break;
     }
+    case SB: {
+      Format(instr, "sb 'rt, 'imms('rs)");
+      break;
+    }
+    case SH: {
+      Format(instr, "sh 'rt, 'imms('rs)");
+      break;
+    }
+    case SW: {
+      Format(instr, "sw 'rt, 'imms('rs)");
+      break;
+    }
     default: {
       OS::PrintErr("Undecoded instruction: 0x%x\n", instr->InstructionBits());
       UNREACHABLE();
       break;
     }
   }
 }
 
 
 int Disassembler::DecodeInstruction(char* hex_buffer, intptr_t hex_size,
@@ skipping 35 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS