Adds MIPS instructions to simulator, assembler, disassembler

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 202 matching lines @@
     ASSERT(delay_slot_available_);
     ASSERT(buffer_.Load<int32_t>(buffer_.GetPosition() - sizeof(int32_t)) ==
         Instr::kNopInstruction);
     buffer_.Remit<int32_t>();
     delay_slot_available_ = false;
     in_delay_slot_ = true;
     return this;
   }
 
   // CPU instructions.
   void addi(Register rt, Register rs, const Immediate& imm) {

[regis, 2013/03/11 17:31:11]

As discussed, we may never use this instruction, because it traps on overflow.
We will use addiu instead. So you may as well remove support for it.

-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsInt(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDI, rs, rt, imm_value);
   }
 
   void addiu(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsInt(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDIU, rs, rt, imm_value);
   }
 
   void addu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, ADDU);
   }
 
   void and_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, AND);
@@ skipping 14 matching lines @@
   }
 
   void div(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIV);
   }
 
   void divu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
   }
 
+  // Extract bit field.
+  void ext(Register rt, Register rs, int32_t pos, int32_t size) {
+    ASSERT((0 <= pos) && (pos < 32));
+    ASSERT((0 < size) && (size <= 32));
+    ASSERT((0 < pos + size) && (pos + size <= 32));

[regis, 2013/03/11 17:31:11]

You could express these 3 asserts using Utils::IsUint().
int32_t msdb = size - 1;
ASSERT(Utils::IsUint(5, pos));
ASSERT(Utils::IsUint(5, msdb));
ASSERT(Utils::IsUint(5, pos + msdb));

+    EmitRType(SPECIAL3, rs, rt, static_cast<Register>(size - 1), pos, EXT);

[Ivan Posva, 2013/03/11 17:29:04]

Maybe we should have a EmitRType which takes a int32_t instead of a Register in
the 3rd register slot?

+  }
+
+  // Insert bit field.
+  void ins(Register rt, Register rs, int32_t pos, int32_t size) {
+    ASSERT((0 <= pos) && (pos < 32));
+    ASSERT((0 < size) && (size <= 32));
+    ASSERT((0 < pos + size) && (pos + size <= 32));

[regis, 2013/03/11 17:31:11]

ditto

Btw, I am not sure we are going to use ext and ins instructions in Dart.

[zra, 2013/03/11 18:36:06]

If these won't be used, as with addi, I'd be happy to remove them. But maybe it
would be useful for me to get a list of MIPS instructions that are likely to be
needed before I implement any more.

[zra, 2013/03/11 20:00:11]

As discussed, I have removed ext and ins.

+    EmitRType(SPECIAL3, rs, rt,
+              static_cast<Register>(pos + size - 1), pos, INS);
+  }
+
+  void lb(Register rt, const Immediate& off, Register base) {

[Ivan Posva, 2013/03/11 17:29:04]

The correct parameters here should be
void lb(Register rt, const Address& addr)
For an example see ldr in assembler_arm.h.

Don't you think?

[zra, 2013/03/11 18:36:06]

As far as I understand, the addressing modes in MIPS are a bit simpler, but I've
filled out the Address class so we can see what it looks like, anyway. I think
it is a bit cleaner.

+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(LB, base, rt, off_value);
+  }
+
+  void lbu(Register rt, const Immediate& off, Register base) {
+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(LBU, base, rt, off_value);
+  }
+
+  void lh(Register rt, const Immediate& off, Register base) {
+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(LH, base, rt, off_value);
+  }
+
+  void lhu(Register rt, const Immediate& off, Register base) {
+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(LHU, base, rt, off_value);
+  }
+
   void lui(Register rt, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(LUI, R0, rt, imm_value);
   }
 
+  void lw(Register rt, const Immediate& off, Register base) {
+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(LW, base, rt, off_value);
+  }
+
   void mfhi(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFHI);
   }
 
   void mflo(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFLO);
   }
 
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
   void jr(Register rs) {
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, R0, 0, JR);
     Emit(Instr::kNopInstruction);  // Branch delay NOP.
     delay_slot_available_ = true;
   }
 
+  void sb(Register rt, const Immediate& off, Register base) {

[Ivan Posva, 2013/03/11 17:29:04]

ditto.

+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(SB, base, rt, off_value);
+  }
+
+  void sh(Register rt, const Immediate& off, Register base) {
+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(SH, base, rt, off_value);
+  }
+
+  void sw(Register rt, const Immediate& off, Register base) {
+    ASSERT(Utils::IsInt(16, off.value()));
+    uint16_t off_value = static_cast<uint16_t>(off.value());
+    EmitIType(SW, base, rt, off_value);
+  }
+
   void sll(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
   }
 
   // Macros.
   void LoadImmediate(Register rd, int32_t value) {
     lui(rd, Immediate((value >> 16) & 0xffff));
     ori(rd, rd, Immediate(value & 0xffff));
   }
 
@@ skipping 71 matching lines @@
          func << kFunctionShift);
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_