Adds MIPS instructions to simulator, assembler, disassembler

runtime/vm/assembler_mips.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_MIPS_H_
 #define VM_ASSEMBLER_MIPS_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_mips.h directly; use assembler.h instead.
 #endif
@@ skipping 23 matching lines @@
   int32_t value_;
 
   int32_t value() const { return value_; }
 
   friend class Assembler;
 };
 
 
 class Address : public ValueObject {
  public:
-  Address(Register base, int32_t offset) {
-    UNIMPLEMENTED();
-  }
+  Address(Register base, int32_t offset = 0)
+      : ValueObject(), base_(base), offset_(offset) { }
 
   Address(const Address& other)
       : ValueObject(), base_(other.base_), offset_(other.offset_) { }
   Address& operator=(const Address& other) {
     base_ = other.base_;
     offset_ = other.offset_;
     return *this;
   }
 
+  uint32_t encoding() const {
+    ASSERT(Utils::IsInt(16, offset_));
+    uint16_t imm_value = static_cast<uint16_t>(offset_);
+    return (base_ << kRsShift) | imm_value;
+  }
+
  private:
   Register base_;
   int32_t offset_;
 };
 
 
 class FieldAddress : public Address {
  public:
   FieldAddress(Register base, int32_t disp)
       : Address(base, disp - kHeapObjectTag) { }
@@ skipping 147 matching lines @@
     ASSERT(delay_slot_available_);
     ASSERT(buffer_.Load<int32_t>(buffer_.GetPosition() - sizeof(int32_t)) ==
         Instr::kNopInstruction);
     buffer_.Remit<int32_t>();
     delay_slot_available_ = false;
     in_delay_slot_ = true;
     return this;
   }
 
   // CPU instructions.
-  void addi(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
-    uint16_t imm_value = static_cast<uint16_t>(imm.value());
-    EmitIType(ADDI, rs, rt, imm_value);
-  }
-
   void addiu(Register rt, Register rs, const Immediate& imm) {
-    ASSERT(Utils::IsUint(16, imm.value()));
+    ASSERT(Utils::IsInt(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ADDIU, rs, rt, imm_value);
   }
 
   void addu(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, ADDU);
   }
 
   void and_(Register rd, Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, rd, 0, AND);
@@ skipping 14 matching lines @@
   }
 
   void div(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIV);
   }
 
   void divu(Register rs, Register rt) {
     EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
   }
 
+
+  void lb(Register rt, const Address& addr) {
+    EmitLoadStore(LB, rt, addr);
+  }
+
+  void lbu(Register rt, const Address& addr) {
+    EmitLoadStore(LBU, rt, addr);
+  }
+
+  void lh(Register rt, const Address& addr) {
+    EmitLoadStore(LH, rt, addr);
+  }
+
+  void lhu(Register rt, const Address& addr) {
+    EmitLoadStore(LHU, rt, addr);
+  }
+
   void lui(Register rt, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(LUI, R0, rt, imm_value);
   }
 
+  void lw(Register rt, const Address& addr) {
+    EmitLoadStore(LW, rt, addr);
+  }
+
   void mfhi(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFHI);
   }
 
   void mflo(Register rd) {
     EmitRType(SPECIAL, R0, R0, rd, 0, MFLO);
   }
 
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
   void jr(Register rs) {
     ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
     EmitRType(SPECIAL, rs, R0, R0, 0, JR);
     Emit(Instr::kNopInstruction);  // Branch delay NOP.
     delay_slot_available_ = true;
   }
 
+  void sb(Register rt, const Address& addr) {
+    EmitLoadStore(SB, rt, addr);
+  }
+
+  void sh(Register rt, const Address& addr) {
+    EmitLoadStore(SH, rt, addr);
+  }
+
+  void sw(Register rt, const Address& addr) {
+    EmitLoadStore(SW, rt, addr);
+  }
+
   void sll(Register rd, Register rt, int sa) {
     EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
   }
 
   // Macros.
   void LoadImmediate(Register rd, int32_t value) {
     lui(rd, Immediate((value >> 16) & 0xffff));
     ori(rd, rd, Immediate(value & 0xffff));
   }
 
@@ skipping 35 matching lines @@
   void EmitIType(Opcode opcode,
                  Register rs,
                  Register rt,
                  uint16_t imm) {
     Emit(opcode << kOpcodeShift |
          rs << kRsShift |
          rt << kRtShift |
          imm);
   }
 
+  void EmitLoadStore(Opcode opcode, Register rt,
+                     const Address &addr) {
+    Emit(opcode << kOpcodeShift |
+         rt << kRtShift |
+         addr.encoding());
+  }
+
   void EmitRegImmType(Opcode opcode,
                       Register rs,
                       RtRegImm code,
                       uint16_t imm) {
     Emit(opcode << kOpcodeShift |
          rs << kRsShift |
          code << kRtShift |
          imm);
   }
 
@@ skipping 16 matching lines @@
          func << kFunctionShift);
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_MIPS_H_