Decode ic data and arguments descriptor passed in calls on ARM.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 153 matching lines @@
                      type << kTypeShift |
                      static_cast<int32_t>(opcode) << kOpcodeShift |
                      set_cc << kSShift |
                      static_cast<int32_t>(rn) << kRnShift |
                      static_cast<int32_t>(rd) << kRdShift |
                      so.encoding();
   Emit(encoding);
 }
 
 
-void Assembler::EmitType5(Condition cond, int offset, bool link) {
+void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      5 << kTypeShift |
                      (link ? 1 : 0) << kLinkShift;
   Emit(Assembler::EncodeBranchOffset(offset, encoding));
 }
 
 
 void Assembler::EmitMemOp(Condition cond,
                           bool load,
@@ skipping 1043 matching lines @@
 
 
 void Assembler::Drop(intptr_t stack_elements) {
   ASSERT(stack_elements >= 0);
   if (stack_elements > 0) {
     AddImmediate(SP, SP, stack_elements * kWordSize);
   }
 }
 
 
+// Uses a code sequence that can easily be decoded.
+void Assembler::LoadWordFromPoolOffset(Register rd, int32_t offset) {
+  ASSERT(rd != PP);
+  int32_t offset_mask = 0;
+  if (Address::CanHoldLoadOffset(kLoadWord, offset, &offset_mask)) {
+    ldr(rd, Address(PP, offset));
+  } else {
+    int32_t offset_hi = offset & ~offset_mask;  // signed
+    uint32_t offset_lo = offset & offset_mask;  // unsigned
+    // Inline a simplified version of AddImmediate(rd, PP, offset_hi).
+    ShifterOperand shifter_op;
+    if (ShifterOperand::CanHold(offset_hi, &shifter_op)) {
+      add(rd, PP, shifter_op);
+    } else {
+      movw(rd, Utils::Low16Bits(offset_hi));
+      const uint16_t value_high = Utils::High16Bits(offset_hi);
+      if (value_high != 0) {
+        movt(rd, value_high);
+      }
+      add(rd, PP, ShifterOperand(LR));
+    }
+    ldr(rd, Address(rd, offset_lo));
+  }
+}
+
+
 void Assembler::LoadObject(Register rd, const Object& object) {
   if (object.IsNull() ||
       object.IsSmi() ||
       (object.raw() == Bool::True().raw()) ||
       (object.raw() == Bool::False().raw())) {
     // This object is never relocated; do not use object pool.
     LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()));
     return;
   }
   const int32_t offset =
       Array::data_offset() + 4*AddObject(object) - kHeapObjectTag;
-  int32_t offset_mask = 0;
-  if (Address::CanHoldLoadOffset(kLoadWord, offset, &offset_mask)) {
-    ldr(rd, Address(PP, offset));
-  } else {
-    int32_t offset_hi = offset & ~offset_mask;  // signed
-    uint32_t offset_lo = offset & offset_mask;  // unsigned
-    AddImmediate(rd, PP, offset_hi);
-    ldr(rd, Address(rd, offset_lo));
-  }
+  LoadWordFromPoolOffset(rd, offset);
 }
 
 
 void Assembler::PushObject(const Object& object) {
   LoadObject(IP, object);
   Push(IP);
 }
 
 
 void Assembler::Bind(Label* label) {
@@ skipping 151 matching lines @@
 }
 
 
 void Assembler::BranchLinkPatchable(const ExternalLabel* label) {
   // Make sure that class CallPattern is able to patch the label referred
   // to by this code sequence.
   // For added code robustness, use 'blx lr' in a patchable sequence and
   // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors).
   const int32_t offset =
       Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag;
-  int32_t offset_mask = 0;
-  if (Address::CanHoldLoadOffset(kLoadWord, offset, &offset_mask)) {
-    ldr(LR, Address(PP, offset));
-  } else {
-    int32_t offset_hi = offset & ~offset_mask;  // signed
-    uint32_t offset_lo = offset & offset_mask;  // unsigned
-    // Inline a simplified version of AddImmediate(LR, CP, offset_hi).
-    ShifterOperand shifter_op;
-    if (ShifterOperand::CanHold(offset_hi, &shifter_op)) {
-      add(LR, PP, shifter_op);
-    } else {
-      movw(LR, Utils::Low16Bits(offset_hi));
-      const uint16_t value_high = Utils::High16Bits(offset_hi);
-      if (value_high != 0) {
-        movt(LR, value_high);
-      }
-      add(LR, PP, ShifterOperand(LR));
-    }
-    ldr(LR, Address(LR, offset_lo));
-  }
+  LoadWordFromPoolOffset(LR, offset);
   blx(LR);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::BranchLinkStore(const ExternalLabel* label, Address ad) {
   // TODO(regis): Revisit this code sequence.
   LoadImmediate(IP, label->address());  // Target address is never patched.
   str(PC, ad);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
-void Assembler::BranchLinkOffset(Register base, int offset) {
+void Assembler::BranchLinkOffset(Register base, int32_t offset) {
   ASSERT(base != PC);
   ASSERT(base != IP);
-  int32_t offset_mask = 0;
-  if (Address::CanHoldLoadOffset(kLoadWord, offset, &offset_mask)) {
-    ldr(IP, Address(base, offset));
-  } else {
-    int offset_hi = offset & ~offset_mask;
-    int offset_lo = offset & offset_mask;
-    ShifterOperand offset_hi_op;
-    if (ShifterOperand::CanHold(offset_hi, &offset_hi_op)) {
-      add(IP, base, offset_hi_op);
-      ldr(IP, Address(IP, offset_lo));
-    } else {
-      LoadImmediate(IP, offset_hi);
-      add(IP, IP, ShifterOperand(base));
-      ldr(IP, Address(IP, offset_lo));
-    }
-  }
+  LoadFromOffset(kLoadWord, IP, base, offset);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     mov(rd, shifter_op, cond);
   } else if (ShifterOperand::CanHold(~value, &shifter_op)) {
     mvn(rd, shifter_op, cond);
@@ skipping 418 matching lines @@
   // 'unstop' and continue execution in the simulator or jump to the next
   // instruction in gdb.
   Label stop;
   b(&stop);
   Emit(reinterpret_cast<int32_t>(message));
   Bind(&stop);
   svc(kStopMessageSvcCode);
 }
 
 
-int32_t Assembler::EncodeBranchOffset(int offset, int32_t inst) {
+int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
   // The offset is off by 8 due to the way the ARM CPUs read PC.
   offset -= 8;
   ASSERT(Utils::IsAligned(offset, 4));
   ASSERT(Utils::IsInt(Utils::CountOneBits(kBranchOffsetMask), offset));
 
   // Properly preserve only the bits supported in the instruction.
   offset >>= 2;
   offset &= kBranchOffsetMask;
   return (inst & ~kBranchOffsetMask) | offset;
 }
@@ skipping 34 matching lines @@
   // Do not reuse an existing entry, since each reference may be patched
   // independently.
   object_pool_.Add(smi);
   return object_pool_.Length() - 1;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM