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Issue 1248303002: Unify runtime-style IC functions with Runtime intrinsics (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Make mips work Created 5 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 5
6 #include "src/v8.h" 6 #include "src/v8.h"
7 7
8 #if V8_TARGET_ARCH_MIPS 8 #if V8_TARGET_ARCH_MIPS
9 9
10 #include "src/codegen.h" 10 #include "src/codegen.h"
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313 // The return address is in ra. 313 // The return address is in ra.
314 Isolate* isolate = masm->isolate(); 314 Isolate* isolate = masm->isolate();
315 315
316 DCHECK(!AreAliased(t0, t1, LoadWithVectorDescriptor::SlotRegister(), 316 DCHECK(!AreAliased(t0, t1, LoadWithVectorDescriptor::SlotRegister(),
317 LoadWithVectorDescriptor::VectorRegister())); 317 LoadWithVectorDescriptor::VectorRegister()));
318 __ IncrementCounter(isolate->counters()->load_miss(), 1, t0, t1); 318 __ IncrementCounter(isolate->counters()->load_miss(), 1, t0, t1);
319 319
320 LoadIC_PushArgs(masm); 320 LoadIC_PushArgs(masm);
321 321
322 // Perform tail call to the entry. 322 // Perform tail call to the entry.
323 ExternalReference ref = ExternalReference(IC_Utility(kLoadIC_Miss), isolate);
324 int arg_count = 4; 323 int arg_count = 4;
325 __ TailCallExternalReference(ref, arg_count, 1); 324 __ TailCallRuntime(Runtime::kLoadIC_Miss, arg_count, 1);
326 } 325 }
327 326
328 327
329 void LoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm, 328 void LoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm,
330 LanguageMode language_mode) { 329 LanguageMode language_mode) {
331 // The return address is in ra. 330 // The return address is in ra.
332 331
333 __ mov(LoadIC_TempRegister(), LoadDescriptor::ReceiverRegister()); 332 __ mov(LoadIC_TempRegister(), LoadDescriptor::ReceiverRegister());
334 __ Push(LoadIC_TempRegister(), LoadDescriptor::NameRegister()); 333 __ Push(LoadIC_TempRegister(), LoadDescriptor::NameRegister());
335 334
336 // Do tail-call to runtime routine. 335 // Do tail-call to runtime routine.
337 __ TailCallRuntime(is_strong(language_mode) ? Runtime::kGetPropertyStrong 336 __ TailCallRuntime(is_strong(language_mode) ? Runtime::kGetPropertyStrong
338 : Runtime::kGetProperty, 337 : Runtime::kGetProperty,
339 2, 1); 338 2, 1);
340 } 339 }
341 340
342 341
343 void KeyedLoadIC::GenerateMiss(MacroAssembler* masm) { 342 void KeyedLoadIC::GenerateMiss(MacroAssembler* masm) {
344 // The return address is in ra. 343 // The return address is in ra.
345 Isolate* isolate = masm->isolate(); 344 Isolate* isolate = masm->isolate();
346 345
347 DCHECK(!AreAliased(t0, t1, LoadWithVectorDescriptor::SlotRegister(), 346 DCHECK(!AreAliased(t0, t1, LoadWithVectorDescriptor::SlotRegister(),
348 LoadWithVectorDescriptor::VectorRegister())); 347 LoadWithVectorDescriptor::VectorRegister()));
349 __ IncrementCounter(isolate->counters()->keyed_load_miss(), 1, t0, t1); 348 __ IncrementCounter(isolate->counters()->keyed_load_miss(), 1, t0, t1);
350 349
351 LoadIC_PushArgs(masm); 350 LoadIC_PushArgs(masm);
352 351
353 // Perform tail call to the entry. 352 // Perform tail call to the entry.
354 ExternalReference ref =
355 ExternalReference(IC_Utility(kKeyedLoadIC_Miss), isolate);
356
357 int arg_count = 4; 353 int arg_count = 4;
358 __ TailCallExternalReference(ref, arg_count, 1); 354 __ TailCallRuntime(Runtime::kKeyedLoadIC_Miss, arg_count, 1);
359 } 355 }
360 356
361 357
362 void KeyedLoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm, 358 void KeyedLoadIC::GenerateRuntimeGetProperty(MacroAssembler* masm,
363 LanguageMode language_mode) { 359 LanguageMode language_mode) {
364 // The return address is in ra. 360 // The return address is in ra.
365 361
366 __ Push(LoadDescriptor::ReceiverRegister(), LoadDescriptor::NameRegister()); 362 __ Push(LoadDescriptor::ReceiverRegister(), LoadDescriptor::NameRegister());
367 363
368 // Do tail-call to runtime routine. 364 // Do tail-call to runtime routine.
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744 __ bind(&miss); 740 __ bind(&miss);
745 GenerateMiss(masm); 741 GenerateMiss(masm);
746 } 742 }
747 743
748 744
749 void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) { 745 void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
750 // Push receiver, key and value for runtime call. 746 // Push receiver, key and value for runtime call.
751 __ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(), 747 __ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
752 StoreDescriptor::ValueRegister()); 748 StoreDescriptor::ValueRegister());
753 749
754 ExternalReference ref = 750 __ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1);
755 ExternalReference(IC_Utility(kKeyedStoreIC_Miss), masm->isolate());
756 __ TailCallExternalReference(ref, 3, 1);
757 } 751 }
758 752
759 753
760 void StoreIC::GenerateMegamorphic(MacroAssembler* masm) { 754 void StoreIC::GenerateMegamorphic(MacroAssembler* masm) {
761 Register receiver = StoreDescriptor::ReceiverRegister(); 755 Register receiver = StoreDescriptor::ReceiverRegister();
762 Register name = StoreDescriptor::NameRegister(); 756 Register name = StoreDescriptor::NameRegister();
763 DCHECK(receiver.is(a1)); 757 DCHECK(receiver.is(a1));
764 DCHECK(name.is(a2)); 758 DCHECK(name.is(a2));
765 DCHECK(StoreDescriptor::ValueRegister().is(a0)); 759 DCHECK(StoreDescriptor::ValueRegister().is(a0));
766 760
767 // Get the receiver from the stack and probe the stub cache. 761 // Get the receiver from the stack and probe the stub cache.
768 Code::Flags flags = Code::RemoveTypeAndHolderFromFlags( 762 Code::Flags flags = Code::RemoveTypeAndHolderFromFlags(
769 Code::ComputeHandlerFlags(Code::STORE_IC)); 763 Code::ComputeHandlerFlags(Code::STORE_IC));
770 masm->isolate()->stub_cache()->GenerateProbe( 764 masm->isolate()->stub_cache()->GenerateProbe(
771 masm, Code::STORE_IC, flags, false, receiver, name, a3, t0, t1, t2); 765 masm, Code::STORE_IC, flags, false, receiver, name, a3, t0, t1, t2);
772 766
773 // Cache miss: Jump to runtime. 767 // Cache miss: Jump to runtime.
774 GenerateMiss(masm); 768 GenerateMiss(masm);
775 } 769 }
776 770
777 771
778 void StoreIC::GenerateMiss(MacroAssembler* masm) { 772 void StoreIC::GenerateMiss(MacroAssembler* masm) {
779 __ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(), 773 __ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
780 StoreDescriptor::ValueRegister()); 774 StoreDescriptor::ValueRegister());
781 // Perform tail call to the entry. 775 // Perform tail call to the entry.
782 ExternalReference ref = 776 __ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1);
783 ExternalReference(IC_Utility(kStoreIC_Miss), masm->isolate());
784 __ TailCallExternalReference(ref, 3, 1);
785 } 777 }
786 778
787 779
788 void StoreIC::GenerateNormal(MacroAssembler* masm) { 780 void StoreIC::GenerateNormal(MacroAssembler* masm) {
789 Label miss; 781 Label miss;
790 Register receiver = StoreDescriptor::ReceiverRegister(); 782 Register receiver = StoreDescriptor::ReceiverRegister();
791 Register name = StoreDescriptor::NameRegister(); 783 Register name = StoreDescriptor::NameRegister();
792 Register value = StoreDescriptor::ValueRegister(); 784 Register value = StoreDescriptor::ValueRegister();
793 Register dictionary = a3; 785 Register dictionary = a3;
794 DCHECK(receiver.is(a1)); 786 DCHECK(receiver.is(a1));
(...skipping 105 matching lines...) Expand 10 before | Expand all | Expand 10 after
900 patcher.ChangeBranchCondition(ne); 892 patcher.ChangeBranchCondition(ne);
901 } else { 893 } else {
902 DCHECK(Assembler::IsBne(branch_instr)); 894 DCHECK(Assembler::IsBne(branch_instr));
903 patcher.ChangeBranchCondition(eq); 895 patcher.ChangeBranchCondition(eq);
904 } 896 }
905 } 897 }
906 } // namespace internal 898 } // namespace internal
907 } // namespace v8 899 } // namespace v8
908 900
909 #endif // V8_TARGET_ARCH_MIPS 901 #endif // V8_TARGET_ARCH_MIPS
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