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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #include "vm/globals.h" // NOLINT | 5 #include "vm/globals.h" // NOLINT |
6 #if defined(TARGET_ARCH_MIPS) | 6 #if defined(TARGET_ARCH_MIPS) |
7 | 7 |
8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
9 #include "vm/longjump.h" | 9 #include "vm/longjump.h" |
10 #include "vm/runtime_entry.h" | 10 #include "vm/runtime_entry.h" |
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878 AddImmediate(TMP, 1); | 878 AddImmediate(TMP, 1); |
879 sw(TMP, Address(temp_reg, count_field_offset)); | 879 sw(TMP, Address(temp_reg, count_field_offset)); |
880 lw(TMP, Address(temp_reg, size_field_offset)); | 880 lw(TMP, Address(temp_reg, size_field_offset)); |
881 addu(TMP, TMP, size_reg); | 881 addu(TMP, TMP, size_reg); |
882 sw(TMP, Address(temp_reg, size_field_offset)); | 882 sw(TMP, Address(temp_reg, size_field_offset)); |
883 } | 883 } |
884 | 884 |
885 | 885 |
886 void Assembler::MaybeTraceAllocation(intptr_t cid, | 886 void Assembler::MaybeTraceAllocation(intptr_t cid, |
887 Register temp_reg, | 887 Register temp_reg, |
888 Label* trace) { | 888 Label* trace, |
| 889 bool inline_isolate) { |
889 ASSERT(cid > 0); | 890 ASSERT(cid > 0); |
890 ASSERT(!in_delay_slot_); | 891 ASSERT(!in_delay_slot_); |
891 ASSERT(temp_reg != kNoRegister); | 892 ASSERT(temp_reg != kNoRegister); |
892 ASSERT(temp_reg != TMP); | 893 ASSERT(temp_reg != TMP); |
893 intptr_t state_offset; | 894 intptr_t state_offset = ClassTable::StateOffsetFor(cid); |
894 ClassTable* class_table = Isolate::Current()->class_table(); | 895 if (inline_isolate) { |
895 ClassHeapStats** table_ptr = | 896 ClassTable* class_table = Isolate::Current()->class_table(); |
896 class_table->StateAddressFor(cid, &state_offset); | 897 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid); |
897 if (cid < kNumPredefinedCids) { | 898 if (cid < kNumPredefinedCids) { |
898 LoadImmediate(temp_reg, reinterpret_cast<uword>(*table_ptr) + state_offset); | 899 LoadImmediate(temp_reg, |
| 900 reinterpret_cast<uword>(*table_ptr) + state_offset); |
| 901 } else { |
| 902 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr)); |
| 903 lw(temp_reg, Address(temp_reg, 0)); |
| 904 AddImmediate(temp_reg, state_offset); |
| 905 } |
899 } else { | 906 } else { |
900 LoadImmediate(temp_reg, reinterpret_cast<uword>(table_ptr)); | 907 LoadIsolate(temp_reg); |
901 lw(temp_reg, Address(temp_reg, 0)); | 908 intptr_t table_offset = |
| 909 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); |
| 910 lw(temp_reg, Address(temp_reg, table_offset)); |
902 AddImmediate(temp_reg, state_offset); | 911 AddImmediate(temp_reg, state_offset); |
903 } | 912 } |
904 lw(temp_reg, Address(temp_reg, 0)); | 913 lw(temp_reg, Address(temp_reg, 0)); |
905 andi(CMPRES1, temp_reg, Immediate(ClassHeapStats::TraceAllocationMask())); | 914 andi(CMPRES1, temp_reg, Immediate(ClassHeapStats::TraceAllocationMask())); |
906 bne(CMPRES1, ZR, trace); | 915 bne(CMPRES1, ZR, trace); |
907 } | 916 } |
908 | 917 |
909 | 918 |
910 void Assembler::TryAllocate(const Class& cls, | 919 void Assembler::TryAllocate(const Class& cls, |
911 Label* failure, | 920 Label* failure, |
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1267 Label stop; | 1276 Label stop; |
1268 b(&stop); | 1277 b(&stop); |
1269 Emit(reinterpret_cast<int32_t>(message)); | 1278 Emit(reinterpret_cast<int32_t>(message)); |
1270 Bind(&stop); | 1279 Bind(&stop); |
1271 break_(Instr::kStopMessageCode); | 1280 break_(Instr::kStopMessageCode); |
1272 } | 1281 } |
1273 | 1282 |
1274 } // namespace dart | 1283 } // namespace dart |
1275 | 1284 |
1276 #endif // defined TARGET_ARCH_MIPS | 1285 #endif // defined TARGET_ARCH_MIPS |
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