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Side by Side Diff: src/IceTargetLoweringARM32.h

Issue 1246013004: Make ARM RegNames[] static like X86 (no ARM syms in X86-only build). (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 5 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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382 382
383 TargetARM32Features CPUFeatures; 383 TargetARM32Features CPUFeatures;
384 bool UsesFramePointer = false; 384 bool UsesFramePointer = false;
385 bool NeedsStackAlignment = false; 385 bool NeedsStackAlignment = false;
386 bool MaybeLeafFunc = true; 386 bool MaybeLeafFunc = true;
387 size_t SpillAreaSizeBytes = 0; 387 size_t SpillAreaSizeBytes = 0;
388 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; 388 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
389 llvm::SmallBitVector ScratchRegs; 389 llvm::SmallBitVector ScratchRegs;
390 llvm::SmallBitVector RegsUsed; 390 llvm::SmallBitVector RegsUsed;
391 VarList PhysicalRegisters[IceType_NUM]; 391 VarList PhysicalRegisters[IceType_NUM];
392 static IceString RegNames[];
393 392
394 /// Helper class that understands the Calling Convention and register 393 /// Helper class that understands the Calling Convention and register
395 /// assignments. The first few integer type parameters can use r0-r3, 394 /// assignments. The first few integer type parameters can use r0-r3,
396 /// regardless of their position relative to the floating-point/vector 395 /// regardless of their position relative to the floating-point/vector
397 /// arguments in the argument list. Floating-point and vector arguments 396 /// arguments in the argument list. Floating-point and vector arguments
398 /// can use q0-q3 (aka d0-d7, s0-s15). Technically, arguments that can 397 /// can use q0-q3 (aka d0-d7, s0-s15). Technically, arguments that can
399 /// start with registers but extend beyond the available registers can be 398 /// start with registers but extend beyond the available registers can be
400 /// split between the registers and the stack. However, this is typically 399 /// split between the registers and the stack. However, this is typically
401 /// for passing GPR structs by value, and PNaCl transforms expand this out. 400 /// for passing GPR structs by value, and PNaCl transforms expand this out.
402 /// 401 ///
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461 460
462 private: 461 private:
463 ~TargetHeaderARM32() = default; 462 ~TargetHeaderARM32() = default;
464 463
465 TargetARM32Features CPUFeatures; 464 TargetARM32Features CPUFeatures;
466 }; 465 };
467 466
468 } // end of namespace Ice 467 } // end of namespace Ice
469 468
470 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H 469 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H
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