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Side by Side Diff: src/IceTargetLoweringARM32.cpp

Issue 1246013004: Make ARM RegNames[] static like X86 (no ARM syms in X86-only build). (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 5 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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341 } 341 }
342 } 342 }
343 343
344 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) { 344 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
345 if (InstARM32Br *Br = llvm::dyn_cast<InstARM32Br>(I)) { 345 if (InstARM32Br *Br = llvm::dyn_cast<InstARM32Br>(I)) {
346 return Br->optimizeBranch(NextNode); 346 return Br->optimizeBranch(NextNode);
347 } 347 }
348 return false; 348 return false;
349 } 349 }
350 350
351 IceString TargetARM32::RegNames[] = {
352 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
353 isFP) \
354 name,
355 REGARM32_TABLE
356 #undef X
357 };
358
359 IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const { 351 IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
360 assert(RegNum < RegARM32::Reg_NUM); 352 assert(RegNum < RegARM32::Reg_NUM);
361 (void)Ty; 353 (void)Ty;
354 static const char *RegNames[] = {
355 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
356 isFP) \
357 name,
358 REGARM32_TABLE
359 #undef X
360 };
361
362 return RegNames[RegNum]; 362 return RegNames[RegNum];
363 } 363 }
364 364
365 Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) { 365 Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
366 if (Ty == IceType_void) 366 if (Ty == IceType_void)
367 Ty = IceType_i32; 367 Ty = IceType_i32;
368 if (PhysicalRegisters[Ty].empty()) 368 if (PhysicalRegisters[Ty].empty())
369 PhysicalRegisters[Ty].resize(RegARM32::Reg_NUM); 369 PhysicalRegisters[Ty].resize(RegARM32::Reg_NUM);
370 assert(RegNum < PhysicalRegisters[Ty].size()); 370 assert(RegNum < PhysicalRegisters[Ty].size());
371 Variable *Reg = PhysicalRegisters[Ty][RegNum]; 371 Variable *Reg = PhysicalRegisters[Ty][RegNum];
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2764 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n"; 2764 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n";
2765 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) { 2765 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
2766 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n"; 2766 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n";
2767 } 2767 }
2768 // Technically R9 is used for TLS with Sandboxing, and we reserve it. 2768 // Technically R9 is used for TLS with Sandboxing, and we reserve it.
2769 // However, for compatibility with current NaCl LLVM, don't claim that. 2769 // However, for compatibility with current NaCl LLVM, don't claim that.
2770 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; 2770 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n";
2771 } 2771 }
2772 2772
2773 } // end of namespace Ice 2773 } // end of namespace Ice
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