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Issue 12459005: Adds muls, sdiv, udiv instructions to ARM simulator, assembler, disassembler (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 9 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include <math.h> // for isnan. 5 #include <math.h> // for isnan.
6 #include <setjmp.h> 6 #include <setjmp.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 8
9 #include "vm/globals.h" 9 #include "vm/globals.h"
10 #if defined(TARGET_ARCH_ARM) 10 #if defined(TARGET_ARCH_ARM)
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1989 if (instr->HasL()) { 1989 if (instr->HasL()) {
1990 set_register(rd, ReadW(addr, instr)); 1990 set_register(rd, ReadW(addr, instr));
1991 } else { 1991 } else {
1992 WriteW(addr, get_register(rd), instr); 1992 WriteW(addr, get_register(rd), instr);
1993 } 1993 }
1994 } 1994 }
1995 } 1995 }
1996 } 1996 }
1997 1997
1998 1998
1999 void Simulator::DoDivision(Instr* instr) {
2000 ASSERT(CPUFeatures::integer_division_supported());
2001 Register rd = instr->RdField();
2002 Register rn = instr->RnField();
2003 Register rm = instr->RmField();
2004
2005 // TODO(zra): Does the hardware trap on divide-by-zero?
2006 // Revisit when we test on ARM hardware.
2007 if (get_register(rm) == 0) {
2008 set_register(rd, 0);
2009 return;
2010 }
2011
2012 if (instr->Bit(21) == 1) {
2013 // unsigned division.
2014 uint32_t rn_val = static_cast<uint32_t>(get_register(rn));
2015 uint32_t rm_val = static_cast<uint32_t>(get_register(rm));
2016 uint32_t result = rn_val / rm_val;
2017 set_register(rd, static_cast<int32_t>(result));
2018 } else {
2019 // signed division.
2020 int32_t rn_val = get_register(rn);
2021 int32_t rm_val = get_register(rm);
2022 int32_t result;
2023 if ((rn_val == static_cast<int32_t>(0x80000000)) &&
2024 (rm_val == static_cast<int32_t>(0xffffffff))) {
2025 result = 0x80000000;
2026 } else {
2027 result = rn_val / rm_val;
2028 }
2029 set_register(rd, result);
2030 }
2031 }
2032
2033
1999 void Simulator::DecodeType3(Instr* instr) { 2034 void Simulator::DecodeType3(Instr* instr) {
2035 if (instr->IsDivision()) {
2036 DoDivision(instr);
2037 return;
2038 }
2000 Register rd = instr->RdField(); 2039 Register rd = instr->RdField();
2001 Register rn = instr->RnField(); 2040 Register rn = instr->RnField();
2002 int32_t rn_val = get_register(rn); 2041 int32_t rn_val = get_register(rn);
2003 bool shifter_carry_out = 0; 2042 bool shifter_carry_out = 0;
2004 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out); 2043 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2005 uword addr = 0; 2044 uword addr = 0;
2006 bool write_back = false; 2045 bool write_back = false;
2007 switch (instr->PUField()) { 2046 switch (instr->PUField()) {
2008 case 0: { 2047 case 0: {
2009 // Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm"); 2048 // Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
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2807 // isolate->ChangeStateToGeneratedCode(); 2846 // isolate->ChangeStateToGeneratedCode();
2808 set_register(kExceptionObjectReg, bit_cast<int32_t>(object.raw())); 2847 set_register(kExceptionObjectReg, bit_cast<int32_t>(object.raw()));
2809 buf->Longjmp(); 2848 buf->Longjmp();
2810 } 2849 }
2811 2850
2812 } // namespace dart 2851 } // namespace dart
2813 2852
2814 #endif // !defined(HOST_ARCH_ARM) 2853 #endif // !defined(HOST_ARCH_ARM)
2815 2854
2816 #endif // defined TARGET_ARCH_ARM 2855 #endif // defined TARGET_ARCH_ARM
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