Adds muls, sdiv, udiv instructions to ARM simulator, assembler, disassembler

runtime/vm/assembler_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM_H_
 #define VM_ASSEMBLER_ARM_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm.h directly; use assembler.h instead.
 #endif
@@ skipping 372 matching lines @@
   void mvn(Register rd, ShifterOperand so, Condition cond = AL);
   void mvns(Register rd, ShifterOperand so, Condition cond = AL);
 
   // Miscellaneous data-processing instructions.
   void clz(Register rd, Register rm, Condition cond = AL);
   void movw(Register rd, uint16_t imm16, Condition cond = AL);
   void movt(Register rd, uint16_t imm16, Condition cond = AL);
 
   // Multiply instructions.
   void mul(Register rd, Register rn, Register rm, Condition cond = AL);
+  void muls(Register rd, Register rn, Register rm, Condition cond = AL);
   void mla(Register rd, Register rn, Register rm, Register ra,
            Condition cond = AL);
   void mls(Register rd, Register rn, Register rm, Register ra,
            Condition cond = AL);
   void umull(Register rd_lo, Register rd_hi, Register rn, Register rm,
              Condition cond = AL);
 
+  // Division instructions.
+  void sdiv(Register rd, Register rn, Register rm, Condition cond = AL);
+  void udiv(Register rd, Register rn, Register rm, Condition cond = AL);
+
   // Load/store instructions.
   void ldr(Register rd, Address ad, Condition cond = AL);
   void str(Register rd, Address ad, Condition cond = AL);
 
   void ldrb(Register rd, Address ad, Condition cond = AL);
   void strb(Register rd, Address ad, Condition cond = AL);
 
   void ldrh(Register rd, Address ad, Condition cond = AL);
   void strh(Register rd, Address ad, Condition cond = AL);
 
@@ skipping 289 matching lines @@
                          Register rm,
                          ShifterOperand so);
 
   void EmitMulOp(Condition cond,
                  int32_t opcode,
                  Register rd,
                  Register rn,
                  Register rm,
                  Register rs);
 
+  void EmitDivOp(Condition cond,
+                 int32_t opcode,
+                 Register rd,
+                 Register rn,
+                 Register rm);
+
   void EmitMultiVSMemOp(Condition cond,
                         BlockAddressMode am,
                         bool load,
                         Register base,
                         SRegister start,
                         uint32_t count);
 
   void EmitMultiVDMemOp(Condition cond,
                         BlockAddressMode am,
                         bool load,
@@ skipping 34 matching lines @@
     return *reg1 - *reg2;
   }
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM_H_