Adds muls, sdiv, udiv instructions to ARM simulator, assembler, disassembler

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 441 matching lines @@
 }
 
 
 void Assembler::mul(Register rd, Register rn,
                     Register rm, Condition cond) {
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   EmitMulOp(cond, 0, R0, rd, rn, rm);
 }
 
 
+// Like mul, but sets condition flags.
+void Assembler::muls(Register rd, Register rn,
+                     Register rm, Condition cond) {
+  EmitMulOp(cond, B20, R0, rd, rn, rm);
+}
+
+
 void Assembler::mla(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
   EmitMulOp(cond, B21, ra, rd, rn, rm);
 }
 
 
 void Assembler::mls(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
   EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
 }
 
 
 void Assembler::umull(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
 }
 
 
+void Assembler::EmitDivOp(Condition cond, int32_t opcode,
+                          Register rd, Register rn, Register rm) {
+  ASSERT(CPUFeatures::integer_division_supported());
+  ASSERT(rd != kNoRegister);
+  ASSERT(rn != kNoRegister);
+  ASSERT(rm != kNoRegister);
+  ASSERT(cond != kNoCondition);
+  int32_t encoding = opcode |
+    (static_cast<int32_t>(cond) << kConditionShift) |
+    (static_cast<int32_t>(rn) << kRnShift) |
+    (static_cast<int32_t>(rd) << kRdShift) |
+    B26 | B25 | B24 | B20 | B4 |
+    (static_cast<int32_t>(rm) << kRmShift);
+  Emit(encoding);
+}
+
+
+void Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
+  EmitDivOp(cond, 0, rd, rn, rm);
+}
+
+
+void Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
+  EmitDivOp(cond, B21 , rd, rn, rm);
+}
+
+
 void Assembler::ldr(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, true, false, rd, ad);
 }
 
 
 void Assembler::str(Register rd, Address ad, Condition cond) {
   EmitMemOp(cond, false, false, rd, ad);
 }
 
 
@@ skipping 1409 matching lines @@
   // Do not reuse an existing entry, since each reference may be patched
   // independently.
   object_pool_.Add(smi);
   return object_pool_.Length() - 1;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM