Rename legalizeToVar to the more accurate legalizeToReg.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1632 matching lines @@
       llvm_unreachable("Call-helper-involved instruction for i64 type \
                        should have already been handled before");
       break;
     }
     return;
   }
   if (isVectorType(Dest->getType())) {
     // TODO: Trap on integer divide and integer modulo by zero.
     // See: https://code.google.com/p/nativeclient/issues/detail?id=3899
     if (llvm::isa<typename Traits::X86OperandMem>(Src1))
-      Src1 = legalizeToVar(Src1);
+      Src1 = legalizeToReg(Src1);
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add: {
       Variable *T = makeReg(Dest->getType());
       _movp(T, Src0);
       _padd(T, Src1);
       _movp(Dest, T);
     } break;
@@ skipping 156 matching lines @@
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     } else {
       _mov(T, Src0);
     }
     _imul(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Shl:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
+      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
     _shl(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Lshr:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
+      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
     _shr(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Ashr:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
+      Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx);
     _sar(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Udiv:
     // div and idiv are the few arithmetic operators that do not allow
     // immediates as the operand.
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     if (isByteSizedArithType(Dest->getType())) {
       Variable *T_ah = nullptr;
       Constant *Zero = Ctx->getConstantZero(IceType_i8);
@@ skipping 324 matching lines @@
   // registers.
   // TODO: Investigate the impact of lowering arguments passed in
   // registers after lowering stack arguments as opposed to the other
   // way around.  Lowering register arguments after stack arguments may
   // reduce register pressure.  On the other hand, lowering register
   // arguments first (before stack arguments) may result in more compact
   // code, as the memory operand displacements may end up being smaller
   // before any stack adjustment is done.
   for (SizeT i = 0, NumXmmArgs = XmmArgs.size(); i < NumXmmArgs; ++i) {
     Variable *Reg =
-        legalizeToVar(XmmArgs[i], Traits::RegisterSet::Reg_xmm0 + i);
+        legalizeToReg(XmmArgs[i], Traits::RegisterSet::Reg_xmm0 + i);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
     Context.insert(InstFakeUse::create(Func, Reg));
   }
   // Generate the call instruction.  Assign its result to a temporary
   // with high register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
@@ skipping 276 matching lines @@
     _cvt(T, Src0RM, Traits::Insts::Cvt::Float2float);
     _mov(Dest, T);
     break;
   }
   case InstCast::Fptosi:
     if (isVectorType(Dest->getType())) {
       assert(Dest->getType() == IceType_v4i32 &&
              Inst->getSrc(0)->getType() == IceType_v4f32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, Traits::Insts::Cvt::Tps2dq);
       _movp(Dest, T);
     } else if (Dest->getType() == IceType_i64) {
       // Use a helper for converting floating-point values to 64-bit
       // integers.  SSE2 appears to have no way to convert from xmm
       // registers to something like the edx:eax register pair, and
       // gcc and clang both want to use x87 instructions complete with
       // temporary manipulation of the status word.  This helper is
       // not needed for x86-64.
@@ skipping 56 matching lines @@
         _and(T_2, Ctx->getConstantInt1(1));
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Sitofp:
     if (isVectorType(Dest->getType())) {
       assert(Dest->getType() == IceType_v4f32 &&
              Inst->getSrc(0)->getType() == IceType_v4i32);
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(Dest->getType());
       _cvt(T, Src0RM, Traits::Insts::Cvt::Dq2ps);
       _movp(Dest, T);
     } else if (Inst->getSrc(0)->getType() == IceType_i64) {
       // Use a helper for x86-32.
       const SizeT MaxSrcs = 1;
       Type DestType = Dest->getType();
       InstCall *Call =
           makeHelperCall(isFloat32Asserting32Or64(DestType) ? H_sitofp_i64_f32
                                                             : H_sitofp_i64_f64,
@@ skipping 194 matching lines @@
       Variable *Src0AsI32 = Func->template makeVariable(stackSlotType());
       // Arguments to functions are required to be at least 32 bits wide.
       lowerCast(InstCast::create(Func, InstCast::Zext, Src0AsI32, Src0));
       Call->addArg(Src0AsI32);
       lowerCall(Call);
     } break;
     case IceType_v8i16:
     case IceType_v16i8:
     case IceType_v4i32:
     case IceType_v4f32: {
-      _movp(Dest, legalizeToVar(Src0));
+      _movp(Dest, legalizeToReg(Src0));
     } break;
     }
     break;
   }
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerExtractElement(
     const InstExtractElement *Inst) {
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   ConstantInteger32 *ElementIndex =
       llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(1));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
   Variable *ExtractedElementR = makeReg(InVectorElementTy);
 
   // TODO(wala): Determine the best lowering sequences for each type.
   bool CanUsePextr = Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
                      InstructionSet >= Traits::SSE4_1;
   if (CanUsePextr && Ty != IceType_v4f32) {
     // Use pextrb, pextrw, or pextrd.
     Constant *Mask = Ctx->getConstantInt32(Index);
-    Variable *SourceVectR = legalizeToVar(SourceVectNotLegalized);
+    Variable *SourceVectR = legalizeToReg(SourceVectNotLegalized);
     _pextr(ExtractedElementR, SourceVectR, Mask);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use pshufd and movd/movss.
     Variable *T = nullptr;
     if (Index) {
       // The shuffle only needs to occur if the element to be extracted
       // is not at the lowest index.
       Constant *Mask = Ctx->getConstantInt32(Index);
       T = makeReg(Ty);
       _pshufd(T, legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem), Mask);
     } else {
-      T = legalizeToVar(SourceVectNotLegalized);
+      T = legalizeToReg(SourceVectNotLegalized);
     }
 
     if (InVectorElementTy == IceType_i32) {
       _movd(ExtractedElementR, T);
     } else { // Ty == IceType_f32
       // TODO(wala): _movss is only used here because _mov does not
       // allow a vector source and a scalar destination.  _mov should be
       // able to be used here.
       // _movss is a binary instruction, so the FakeDef is needed to
       // keep the live range analysis consistent.
       Context.insert(InstFakeDef::create(Func, ExtractedElementR));
       _movss(ExtractedElementR, T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and do the extraction in memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when
     // support for legalizing to mem is implemented.
     Variable *Slot = Func->template makeVariable(Ty);
     Slot->setWeight(RegWeight::Zero);
-    _movp(Slot, legalizeToVar(SourceVectNotLegalized));
+    _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the element in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     typename Traits::X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _mov(ExtractedElementR, Loc);
   }
 
   if (ElementTy == IceType_i1) {
     // Truncate extracted integers to i1s if necessary.
@@ skipping 30 matching lines @@
 
     if (Condition == InstFcmp::True) {
       // makeVectorOfOnes() requires an integer vector type.
       T = makeVectorOfMinusOnes(IceType_v4i32);
     } else if (Condition == InstFcmp::False) {
       T = makeVectorOfZeros(Dest->getType());
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
 
       switch (Condition) {
       default: {
         typename Traits::Cond::CmppsCond Predicate =
             Traits::TableFcmp[Index].Predicate;
         assert(Predicate != Traits::Cond::Cmpps_Invalid);
         T = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
         _cmpps(T, Src1RM, Predicate);
       } break;
@@ skipping 128 matching lines @@
       Src1RM = T1;
     }
 
     Variable *T = makeReg(Ty);
     switch (Condition) {
     default:
       llvm_unreachable("unexpected condition");
       break;
     case InstIcmp::Eq: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpeq(T, Src1RM);
     } break;
     case InstIcmp::Ne: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpeq(T, Src1RM);
       Variable *MinusOne = makeVectorOfMinusOnes(Ty);
       _pxor(T, MinusOne);
     } break;
     case InstIcmp::Ugt:
     case InstIcmp::Sgt: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpgt(T, Src1RM);
     } break;
     case InstIcmp::Uge:
     case InstIcmp::Sge: {
       // !(Src1RM > Src0RM)
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       _movp(T, Src1RM);
       _pcmpgt(T, Src0RM);
       Variable *MinusOne = makeVectorOfMinusOnes(Ty);
       _pxor(T, MinusOne);
     } break;
     case InstIcmp::Ult:
     case InstIcmp::Slt: {
       if (llvm::isa<typename Traits::X86OperandMem>(Src0RM))
-        Src0RM = legalizeToVar(Src0RM);
+        Src0RM = legalizeToReg(Src0RM);
       _movp(T, Src1RM);
       _pcmpgt(T, Src0RM);
     } break;
     case InstIcmp::Ule:
     case InstIcmp::Sle: {
       // !(Src0RM > Src1RM)
       if (llvm::isa<typename Traits::X86OperandMem>(Src1RM))
-        Src1RM = legalizeToVar(Src1RM);
+        Src1RM = legalizeToReg(Src1RM);
       _movp(T, Src0RM);
       _pcmpgt(T, Src1RM);
       Variable *MinusOne = makeVectorOfMinusOnes(Ty);
       _pxor(T, MinusOne);
     } break;
     }
 
     _movp(Dest, T);
     eliminateNextVectorSextInstruction(Dest);
     return;
@@ skipping 74 matching lines @@
       _pinsr(T, ElementRM, Ctx->getConstantInt32(Index));
     _movp(Inst->getDest(), T);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use shufps or movss.
     Variable *ElementR = nullptr;
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
 
     if (InVectorElementTy == IceType_f32) {
       // ElementR will be in an XMM register since it is floating point.
-      ElementR = legalizeToVar(ElementToInsertNotLegalized);
+      ElementR = legalizeToReg(ElementToInsertNotLegalized);
     } else {
       // Copy an integer to an XMM register.
       Operand *T = legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
       ElementR = makeReg(Ty);
       _movd(ElementR, T);
     }
 
     if (Index == 0) {
       Variable *T = makeReg(Ty);
       _movp(T, SourceVectRM);
@@ skipping 43 matching lines @@
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and perform the insertion in
     // memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when
     // support for legalizing to mem is implemented.
     Variable *Slot = Func->template makeVariable(Ty);
     Slot->setWeight(RegWeight::Zero);
-    _movp(Slot, legalizeToVar(SourceVectNotLegalized));
+    _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the position to insert in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     typename Traits::X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
-    _store(legalizeToVar(ElementToInsertNotLegalized), Loc);
+    _store(legalizeToReg(ElementToInsertNotLegalized), Loc);
 
     Variable *T = makeReg(Ty);
     _movp(T, Slot);
     _movp(Inst->getDest(), T);
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerIntrinsicCall(
     const InstIntrinsicCall *Instr) {
@@ skipping 136 matching lines @@
     _mfence();
     return;
   }
   case Intrinsics::Bswap: {
     Variable *Dest = Instr->getDest();
     Operand *Val = Instr->getArg(0);
     // In 32-bit mode, bswap only works on 32-bit arguments, and the
     // argument must be a register. Use rotate left for 16-bit bswap.
     if (Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
-      Variable *T_Lo = legalizeToVar(loOperand(Val));
-      Variable *T_Hi = legalizeToVar(hiOperand(Val));
+      Variable *T_Lo = legalizeToReg(loOperand(Val));
+      Variable *T_Hi = legalizeToReg(hiOperand(Val));
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       _bswap(T_Lo);
       _bswap(T_Hi);
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
     } else if (Val->getType() == IceType_i32) {
-      Variable *T = legalizeToVar(Val);
+      Variable *T = legalizeToReg(Val);
       _bswap(T);
       _mov(Dest, T);
     } else {
       assert(Val->getType() == IceType_i16);
       Constant *Eight = Ctx->getConstantInt16(8);
       Variable *T = nullptr;
       Val = legalize(Val);
       _mov(T, Val);
       _rol(T, Eight);
       _mov(Dest, T);
@@ skipping 57 matching lines @@
   }
   case Intrinsics::Fabs: {
     Operand *Src = legalize(Instr->getArg(0));
     Type Ty = Src->getType();
     Variable *Dest = Instr->getDest();
     Variable *T = makeVectorOfFabsMask(Ty);
     // The pand instruction operates on an m128 memory operand, so if
     // Src is an f32 or f64, we need to make sure it's in a register.
     if (isVectorType(Ty)) {
       if (llvm::isa<typename Traits::X86OperandMem>(Src))
-        Src = legalizeToVar(Src);
+        Src = legalizeToReg(Src);
     } else {
-      Src = legalizeToVar(Src);
+      Src = legalizeToReg(Src);
     }
     _pand(T, Src);
     if (isVectorType(Ty))
       _movp(Dest, T);
     else
       _mov(Dest, T);
     return;
   }
   case Intrinsics::Longjmp: {
     InstCall *Call = makeHelperCall(H_call_longjmp, nullptr, 2);
@@ skipping 109 matching lines @@
     Variable *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   Variable *T_eax = makeReg(Expected->getType(), Traits::RegisterSet::Reg_eax);
   _mov(T_eax, Expected);
   typename Traits::X86OperandMem *Addr =
       formMemoryOperand(Ptr, Expected->getType());
-  Variable *DesiredReg = legalizeToVar(Desired);
+  Variable *DesiredReg = legalizeToReg(Desired);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
 template <class Machine>
 bool TargetX86Base<Machine>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
                                                       Operand *PtrToMem,
                                                       Operand *Expected,
                                                       Operand *Desired) {
@@ skipping 321 matching lines @@
     _xor(T_Dest, ThirtyOne);
   }
   if (Ty == IceType_i32) {
     _mov(Dest, T_Dest);
     return;
   }
   _add(T_Dest, ThirtyTwo);
   Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
   Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
   // Will be using "test" on this, so we need a registerized variable.
-  Variable *SecondVar = legalizeToVar(SecondVal);
+  Variable *SecondVar = legalizeToReg(SecondVal);
   Variable *T_Dest2 = makeReg(IceType_i32);
   if (Cttz) {
     _bsf(T_Dest2, SecondVar);
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, ThirtyOne);
   }
   _test(SecondVar, SecondVar);
   _cmov(T_Dest2, T_Dest, Traits::Cond::Br_e);
   _mov(DestLo, T_Dest2);
@@ skipping 291 matching lines @@
   Func->setError("Phi found in regular instruction list");
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
       Variable *eax =
-          legalizeToVar(loOperand(Src0), Traits::RegisterSet::Reg_eax);
+          legalizeToReg(loOperand(Src0), Traits::RegisterSet::Reg_eax);
       Variable *edx =
-          legalizeToVar(hiOperand(Src0), Traits::RegisterSet::Reg_edx);
+          legalizeToReg(hiOperand(Src0), Traits::RegisterSet::Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
     } else if (isScalarFloatingType(Src0->getType())) {
       _fld(Src0);
     } else if (isVectorType(Src0->getType())) {
-      Reg = legalizeToVar(Src0, Traits::RegisterSet::Reg_xmm0);
+      Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0);
     } else {
       _mov(Reg, Src0, Traits::RegisterSet::Reg_eax);
     }
   }
   // Add a ret instruction even if sandboxing is enabled, because
   // addEpilog explicitly looks for a ret instruction as a marker for
   // where to insert the frame removal instructions.
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function.  Otherwise post-call esp adjustments get dead-code
@@ skipping 159 matching lines @@
 
   if (Ty == IceType_i64) {
     Value = legalizeUndef(Value);
     Operand *ValueHi = legalize(hiOperand(Value), Legal_Reg | Legal_Imm);
     Operand *ValueLo = legalize(loOperand(Value), Legal_Reg | Legal_Imm);
     _store(ValueHi,
            llvm::cast<typename Traits::X86OperandMem>(hiOperand(NewAddr)));
     _store(ValueLo,
            llvm::cast<typename Traits::X86OperandMem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
-    _storep(legalizeToVar(Value), NewAddr);
+    _storep(legalizeToReg(Value), NewAddr);
   } else {
     Value = legalize(Value, Legal_Reg | Legal_Imm);
     _store(Value, NewAddr);
   }
 }
 
 template <class Machine> void TargetX86Base<Machine>::doAddressOptStore() {
   InstStore *Inst = llvm::cast<InstStore>(Context.getCur());
   Operand *Data = Inst->getData();
   Operand *Addr = Inst->getAddr();
@@ skipping 60 matching lines @@
 
     InstJumpTable *JumpTable = Case.getJumpTable();
     Context.insert(JumpTable);
 
     // Make sure the index is a register of the same width as the base
     Variable *Index;
     if (RangeIndex->getType() != getPointerType()) {
       Index = makeReg(getPointerType());
       _movzx(Index, RangeIndex);
     } else {
-      Index = legalizeToVar(RangeIndex);
+      Index = legalizeToReg(RangeIndex);
     }
 
     constexpr RelocOffsetT RelocOffset = 0;
     constexpr bool SuppressMangling = true;
     Constant *Base = Ctx->getConstantSym(RelocOffset, JumpTable->getName(Func),
                                          SuppressMangling);
     Constant *Offset = nullptr;
     uint16_t Shift = typeWidthInBytesLog2(getPointerType());
     // TODO(ascull): remove need for legalize by allowing null base in memop
     auto *MemTarget = Traits::X86OperandMem::create(
-        Func, getPointerType(), legalizeToVar(Base), Offset, Index, Shift);
+        Func, getPointerType(), legalizeToReg(Base), Offset, Index, Shift);
     Variable *Target = nullptr;
     _mov(Target, MemTarget);
     _jmp(Target);
     // TODO(ascull): sandboxing for indirect jump
 
     if (DefaultLabel == nullptr)
       Context.insert(SkipJumpTable);
     return;
   }
   case CaseCluster::Range: {
@@ skipping 23 matching lines @@
   if (!Ctx->getFlags().getUseAdvancedSwitchLowering()) {
     // This implements the most naive possible lowering.
     // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
     Operand *Src0 = Inst->getComparison();
     SizeT NumCases = Inst->getNumCases();
     if (Src0->getType() == IceType_i64) {
       Src0 = legalize(Src0); // get Base/Index into physical registers
       Operand *Src0Lo = loOperand(Src0);
       Operand *Src0Hi = hiOperand(Src0);
       if (NumCases >= 2) {
-        Src0Lo = legalizeToVar(Src0Lo);
-        Src0Hi = legalizeToVar(Src0Hi);
+        Src0Lo = legalizeToReg(Src0Lo);
+        Src0Hi = legalizeToReg(Src0Hi);
       } else {
         Src0Lo = legalize(Src0Lo, Legal_Reg | Legal_Mem);
         Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
       }
       for (SizeT I = 0; I < NumCases; ++I) {
         Constant *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
         Constant *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
         typename Traits::Insts::Label *Label =
             Traits::Insts::Label::create(Func, this);
         _cmp(Src0Lo, ValueLo);
         _br(Traits::Cond::Br_ne, Label);
         _cmp(Src0Hi, ValueHi);
         _br(Traits::Cond::Br_e, Inst->getLabel(I));
         Context.insert(Label);
       }
       _br(Inst->getLabelDefault());
       return;
     }
     // OK, we'll be slightly less naive by forcing Src into a physical
     // register if there are 2 or more uses.
     if (NumCases >= 2)
-      Src0 = legalizeToVar(Src0);
+      Src0 = legalizeToReg(Src0);
     else
       Src0 = legalize(Src0, Legal_Reg | Legal_Mem);
     for (SizeT I = 0; I < NumCases; ++I) {
       Constant *Value = Ctx->getConstantInt32(Inst->getValue(I));
       _cmp(Src0, Value);
       _br(Traits::Cond::Br_e, Inst->getLabel(I));
     }
 
     _br(Inst->getLabelDefault());
     return;
   }
 
   // Group cases together and navigate through them with a binary search
   CaseClusterArray CaseClusters = CaseCluster::clusterizeSwitch(Func, Inst);
   Operand *Src0 = Inst->getComparison();
   CfgNode *DefaultLabel = Inst->getLabelDefault();
 
   assert(CaseClusters.size() != 0); // Should always be at least one
 
   if (Src0->getType() == IceType_i64) {
     Src0 = legalize(Src0); // get Base/Index into physical registers
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     if (CaseClusters.back().getHigh() > UINT32_MAX) {
       // TODO(ascull): handle 64-bit case properly (currently naive version)
       // This might be handled by a higher level lowering of switches.
       SizeT NumCases = Inst->getNumCases();
       if (NumCases >= 2) {
-        Src0Lo = legalizeToVar(Src0Lo);
-        Src0Hi = legalizeToVar(Src0Hi);
+        Src0Lo = legalizeToReg(Src0Lo);
+        Src0Hi = legalizeToReg(Src0Hi);
       } else {
         Src0Lo = legalize(Src0Lo, Legal_Reg | Legal_Mem);
         Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
       }
       for (SizeT I = 0; I < NumCases; ++I) {
         Constant *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
         Constant *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
         typename Traits::Insts::Label *Label =
             Traits::Insts::Label::create(Func, this);
         _cmp(Src0Lo, ValueLo);
@@ skipping 19 matching lines @@
 
   if (CaseClusters.size() == 1) {
     // Jump straight to default if needed. Currently a common case as jump
     // tables occur on their own.
     constexpr bool DoneCmp = false;
     lowerCaseCluster(CaseClusters.front(), Src0, DoneCmp, DefaultLabel);
     return;
   }
 
   // Going to be using multiple times so get it in a register early
-  Variable *Comparison = legalizeToVar(Src0);
+  Variable *Comparison = legalizeToReg(Src0);
 
   // A span is over the clusters
   struct SearchSpan {
     SearchSpan(SizeT Begin, SizeT Size, typename Traits::Insts::Label *Label)
         : Begin(Begin), Size(Size), Label(Label) {}
 
     SizeT Begin;
     SizeT Size;
     typename Traits::Insts::Label *Label;
   };
@@ skipping 89 matching lines @@
 /// pcmpgtd, or cmpps (which produce sign extended results) to the result
 /// of the sext operation.
 template <class Machine>
 void TargetX86Base<Machine>::eliminateNextVectorSextInstruction(
     Variable *SignExtendedResult) {
   if (InstCast *NextCast =
           llvm::dyn_cast_or_null<InstCast>(Context.getNextInst())) {
     if (NextCast->getCastKind() == InstCast::Sext &&
         NextCast->getSrc(0) == SignExtendedResult) {
       NextCast->setDeleted();
-      _movp(NextCast->getDest(), legalizeToVar(SignExtendedResult));
+      _movp(NextCast->getDest(), legalizeToReg(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerUnreachable(
     const InstUnreachable * /*Inst*/) {
   _ud2();
@@ skipping 377 matching lines @@
   assert(RegNum == Variable::NoRegister || Allowed == Legal_Reg);
 
   if (auto Mem = llvm::dyn_cast<typename Traits::X86OperandMem>(From)) {
     // Before doing anything with a Mem operand, we need to ensure
     // that the Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
-      RegBase = legalizeToVar(Base);
+      RegBase = legalizeToReg(Base);
     }
     if (Index) {
-      RegIndex = legalizeToVar(Index);
+      RegIndex = legalizeToReg(Index);
     }
     if (Base != RegBase || Index != RegIndex) {
       Mem = Traits::X86OperandMem::create(Func, Ty, RegBase, Mem->getOffset(),
                                           RegIndex, Mem->getShift(),
                                           Mem->getSegmentRegister());
     }
 
     // For all Memory Operands, we do randomization/pooling here
     From = randomizeOrPoolImmediate(Mem);
 
@@ skipping 58 matching lines @@
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
 template <class Machine>
-Variable *TargetX86Base<Machine>::legalizeToVar(Operand *From, int32_t RegNum) {
+Variable *TargetX86Base<Machine>::legalizeToReg(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
 template <class Machine>
 Operand *TargetX86Base<Machine>::legalizeUndef(Operand *From, int32_t RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero.  Another option is to lower undefs to an
     // uninitialized register; however, using an uninitialized register
@@ skipping 325 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H