Rename legalizeToVar to the more accurate legalizeToReg.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1009 matching lines @@
     _add(T, T, AddAmount);
     alignRegisterPow2(T, Alignment);
     _sub(SP, SP, T);
   }
   _mov(Dest, SP);
 }
 
 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) {
   if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi))
     return;
-  Variable *SrcLoReg = legalizeToVar(SrcLo);
+  Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
     llvm_unreachable("Unexpected type");
   case IceType_i8: {
     Operand *Mask =
         legalize(Ctx->getConstantInt32(0xFF), Legal_Reg | Legal_Flex);
     _tst(SrcLoReg, Mask);
     break;
   }
   case IceType_i16: {
@@ skipping 18 matching lines @@
   _br(Label, CondARM32::NE);
   _trap();
   Context.insert(Label);
 }
 
 void TargetARM32::lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R,
                                Operand *Src1, ExtInstr ExtFunc,
                                DivInstr DivFunc, const char *DivHelperName,
                                bool IsRemainder) {
   div0Check(Dest->getType(), Src1, nullptr);
-  Variable *Src1R = legalizeToVar(Src1);
+  Variable *Src1R = legalizeToReg(Src1);
   Variable *T0R = Src0R;
   Variable *T1R = Src1R;
   if (Dest->getType() != IceType_i32) {
     T0R = makeReg(IceType_i32);
     (this->*ExtFunc)(T0R, Src0R, CondARM32::AL);
     T1R = makeReg(IceType_i32);
     (this->*ExtFunc)(T1R, Src1R, CondARM32::AL);
   }
   if (hasCPUFeature(TargetARM32Features::HWDivArm)) {
     (this->*DivFunc)(T, T0R, T1R, CondARM32::AL);
@@ skipping 76 matching lines @@
       constexpr SizeT MaxSrcs = 2;
       InstCall *Call = makeHelperCall(HelperName, Dest, MaxSrcs);
       Call->addArg(Src0);
       Call->addArg(Src1);
       lowerCall(Call);
       return;
     }
     }
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
-    Variable *Src0RLo = legalizeToVar(loOperand(Src0));
-    Variable *Src0RHi = legalizeToVar(hiOperand(Src0));
+    Variable *Src0RLo = legalizeToReg(loOperand(Src0));
+    Variable *Src0RHi = legalizeToReg(hiOperand(Src0));
     Operand *Src1Lo = loOperand(Src1);
     Operand *Src1Hi = hiOperand(Src1);
     Variable *T_Lo = makeReg(DestLo->getType());
     Variable *T_Hi = makeReg(DestHi->getType());
     switch (Inst->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       return;
     case InstArithmetic::Add:
       Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Flex);
@@ skipping 51 matching lines @@
       //   t.hi =(mla) (b.hi * c.lo) + t.hi
       //   a.lo = t.lo
       //   a.hi = t.hi
       //
       // LLVM's lowering has fewer instructions, but more register pressure:
       // t.lo is live from beginning to end, while GCC delays the two-dest
       // instruction till the end, and kills c.hi immediately.
       Variable *T_Acc = makeReg(IceType_i32);
       Variable *T_Acc1 = makeReg(IceType_i32);
       Variable *T_Hi1 = makeReg(IceType_i32);
-      Variable *Src1RLo = legalizeToVar(Src1Lo);
-      Variable *Src1RHi = legalizeToVar(Src1Hi);
+      Variable *Src1RLo = legalizeToReg(Src1Lo);
+      Variable *Src1RHi = legalizeToReg(Src1Hi);
       _mul(T_Acc, Src0RLo, Src1RHi);
       _mla(T_Acc1, Src1RLo, Src0RHi, T_Acc);
       _umull(T_Lo, T_Hi1, Src0RLo, Src1RLo);
       _add(T_Hi, T_Hi1, T_Acc1);
       _mov(DestLo, T_Lo);
       _mov(DestHi, T_Hi);
       return;
     }
     case InstArithmetic::Shl: {
       // a=b<<c ==>
       // GCC 4.8 does:
       // sub t_c1, c.lo, #32
       // lsl t_hi, b.hi, c.lo
       // orr t_hi, t_hi, b.lo, lsl t_c1
       // rsb t_c2, c.lo, #32
       // orr t_hi, t_hi, b.lo, lsr t_c2
       // lsl t_lo, b.lo, c.lo
       // a.lo = t_lo
       // a.hi = t_hi
       // Can be strength-reduced for constant-shifts, but we don't do
       // that for now.
       // Given the sub/rsb T_C, C.lo, #32, one of the T_C will be negative.
       // On ARM, shifts only take the lower 8 bits of the shift register,
       // and saturate to the range 0-32, so the negative value will
       // saturate to 32.
       Variable *T_Hi = makeReg(IceType_i32);
-      Variable *Src1RLo = legalizeToVar(Src1Lo);
+      Variable *Src1RLo = legalizeToReg(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
       Variable *T_C2 = makeReg(IceType_i32);
       _sub(T_C1, Src1RLo, ThirtyTwo);
       _lsl(T_Hi, Src0RHi, Src1RLo);
       _orr(T_Hi, T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, Src0RLo,
                                                    OperandARM32::LSL, T_C1));
       _rsb(T_C2, Src1RLo, ThirtyTwo);
       _orr(T_Hi, T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, Src0RLo,
                                                    OperandARM32::LSR, T_C2));
@@ skipping 18 matching lines @@
     // lsr t_hi, b.hi, c.lo
     // a.lo = t_lo
     // a.hi = t_hi
     case InstArithmetic::Ashr: {
       // a=b>>c (signed) ==> ...
       // Ashr is similar, but the sub t_c2, c.lo, #32 should set flags,
       // and the next orr should be conditioned on PLUS. The last two
       // right shifts should also be arithmetic.
       bool IsAshr = Inst->getOp() == InstArithmetic::Ashr;
       Variable *T_Lo = makeReg(IceType_i32);
-      Variable *Src1RLo = legalizeToVar(Src1Lo);
+      Variable *Src1RLo = legalizeToReg(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
       Variable *T_C2 = makeReg(IceType_i32);
       _rsb(T_C1, Src1RLo, ThirtyTwo);
       _lsr(T_Lo, Src0RLo, Src1RLo);
       _orr(T_Lo, T_Lo, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
                                                    OperandARM32::LSL, T_C1));
       OperandARM32::ShiftKind RShiftKind;
       CondARM32::Cond Pred;
       if (IsAshr) {
@@ skipping 29 matching lines @@
       llvm_unreachable("Call-helper-involved instruction for i64 type "
                        "should have already been handled before");
       return;
     }
     return;
   } else if (isVectorType(Dest->getType())) {
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   // Dest->getType() is a non-i64 scalar.
-  Variable *Src0R = legalizeToVar(Src0);
+  Variable *Src0R = legalizeToReg(Src0);
   Variable *T = makeReg(Dest->getType());
   // Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
   // difficult to determine (constant may be moved to a register).
   switch (Inst->getOp()) {
   default:
     break;
   case InstArithmetic::Udiv: {
     constexpr bool IsRemainder = false;
     lowerIDivRem(Dest, T, Src0R, Src1, &TargetARM32::_uxt, &TargetARM32::_udiv,
@@ skipping 39 matching lines @@
     return;
   case InstArithmetic::Xor:
     _eor(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Sub:
     _sub(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Mul: {
-    Variable *Src1R = legalizeToVar(Src1RF);
+    Variable *Src1R = legalizeToReg(Src1RF);
     _mul(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Shl:
     _lsl(T, Src0R, Src1RF);
     _mov(Dest, T);
     return;
   case InstArithmetic::Lshr:
     _lsr(T, Src0R, Src1RF);
@@ skipping 68 matching lines @@
 }
 
 void TargetARM32::lowerBr(const InstBr *Inst) {
   if (Inst->isUnconditional()) {
     _br(Inst->getTargetUnconditional());
     return;
   }
   Operand *Cond = Inst->getCondition();
   // TODO(jvoung): Handle folding opportunities.
 
-  Variable *Src0R = legalizeToVar(Cond);
+  Variable *Src0R = legalizeToReg(Cond);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0R, Zero);
   _br(Inst->getTargetTrue(), Inst->getTargetFalse(), CondARM32::NE);
 }
 
 void TargetARM32::lowerCall(const InstCall *Instr) {
   MaybeLeafFunc = false;
   NeedsStackAlignment = true;
 
   // Assign arguments to registers and stack. Also reserve stack.
@@ skipping 73 matching lines @@
       Variable *NewBase = Func->makeVariable(SP->getType());
       lowerArithmetic(
           InstArithmetic::create(Func, InstArithmetic::Add, NewBase, SP, Loc));
       Addr = formMemoryOperand(NewBase, Ty);
     }
     lowerStore(InstStore::create(Func, StackArg.first, Addr));
   }
 
   // Copy arguments to be passed in registers to the appropriate registers.
   for (auto &GPRArg : GPRArgs) {
-    Variable *Reg = legalizeToVar(GPRArg.first, GPRArg.second);
+    Variable *Reg = legalizeToReg(GPRArg.first, GPRArg.second);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
     Context.insert(InstFakeUse::create(Func, Reg));
   }
 
   // Generate the call instruction.  Assign its result to a temporary
   // with high register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
@@ skipping 105 matching lines @@
     } else if (Dest->getType() == IceType_i64) {
       // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       if (Src0->getType() == IceType_i32) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else if (Src0->getType() == IceType_i1) {
-        Variable *Src0R = legalizeToVar(Src0);
+        Variable *Src0R = legalizeToReg(Src0);
         _lsl(T_Lo, Src0R, ShiftAmt);
         _asr(T_Lo, T_Lo, ShiftAmt);
       } else {
-        Variable *Src0R = legalizeToVar(Src0);
+        Variable *Src0R = legalizeToReg(Src0);
         _sxt(T_Lo, Src0R);
       }
       _mov(DestLo, T_Lo);
       Variable *T_Hi = makeReg(DestHi->getType());
       if (Src0->getType() != IceType_i1) {
         _mov(T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, T_Lo,
                                                OperandARM32::ASR, ShiftAmt));
       } else {
         // For i1, the asr instruction is already done above.
         _mov(T_Hi, T_Lo);
       }
       _mov(DestHi, T_Hi);
     } else if (Src0->getType() == IceType_i1) {
       // GPR registers are 32-bit, so just use 31 as dst_bitwidth - 1.
       // lsl t1, src_reg, 31
       // asr t1, t1, 31
       // dst = t1
-      Variable *Src0R = legalizeToVar(Src0);
+      Variable *Src0R = legalizeToReg(Src0);
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
       Variable *T = makeReg(Dest->getType());
       _lsl(T, Src0R, ShiftAmt);
       _asr(T, T, ShiftAmt);
       _mov(Dest, T);
     } else {
       // t1 = sxt src; dst = t1
-      Variable *Src0R = legalizeToVar(Src0);
+      Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _sxt(T, Src0R);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Zext: {
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else if (Dest->getType() == IceType_i64) {
       // t1=uxtb src; dst.lo=t1; dst.hi=0
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       // i32 and i1 can just take up the whole register.
       // i32 doesn't need uxt, while i1 will have an and mask later anyway.
       if (Src0->getType() == IceType_i32 || Src0->getType() == IceType_i1) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else {
-        Variable *Src0R = legalizeToVar(Src0);
+        Variable *Src0R = legalizeToReg(Src0);
         _uxt(T_Lo, Src0R);
       }
       if (Src0->getType() == IceType_i1) {
         Constant *One = Ctx->getConstantInt32(1);
         _and(T_Lo, T_Lo, One);
       }
       _mov(DestLo, T_Lo);
       Variable *T_Hi = makeReg(DestLo->getType());
       _mov(T_Hi, Zero);
       _mov(DestHi, T_Hi);
     } else if (Src0->getType() == IceType_i1) {
       // t = Src0; t &= 1; Dest = t
       Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
       Constant *One = Ctx->getConstantInt32(1);
       Variable *T = makeReg(Dest->getType());
       // Just use _mov instead of _uxt since all registers are 32-bit.
       // _uxt requires the source to be a register so could have required
       // a _mov from legalize anyway.
       _mov(T, Src0RF);
       _and(T, T, One);
       _mov(Dest, T);
     } else {
       // t1 = uxt src; dst = t1
-      Variable *Src0R = legalizeToVar(Src0);
+      Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _uxt(T, Src0R);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else {
@@ skipping 93 matching lines @@
   // perhaps for eq/ne). We could revisit special-casing eq/ne later.
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   Constant *One = Ctx->getConstantInt32(1);
   if (Src0->getType() == IceType_i64) {
     InstIcmp::ICond Conditon = Inst->getCondition();
     size_t Index = static_cast<size_t>(Conditon);
     assert(Index < TableIcmp64Size);
     Variable *Src0Lo, *Src0Hi;
     Operand *Src1LoRF, *Src1HiRF;
     if (TableIcmp64[Index].Swapped) {
-      Src0Lo = legalizeToVar(loOperand(Src1));
-      Src0Hi = legalizeToVar(hiOperand(Src1));
+      Src0Lo = legalizeToReg(loOperand(Src1));
+      Src0Hi = legalizeToReg(hiOperand(Src1));
       Src1LoRF = legalize(loOperand(Src0), Legal_Reg | Legal_Flex);
       Src1HiRF = legalize(hiOperand(Src0), Legal_Reg | Legal_Flex);
     } else {
-      Src0Lo = legalizeToVar(loOperand(Src0));
-      Src0Hi = legalizeToVar(hiOperand(Src0));
+      Src0Lo = legalizeToReg(loOperand(Src0));
+      Src0Hi = legalizeToReg(hiOperand(Src0));
       Src1LoRF = legalize(loOperand(Src1), Legal_Reg | Legal_Flex);
       Src1HiRF = legalize(hiOperand(Src1), Legal_Reg | Legal_Flex);
     }
     Variable *T = makeReg(IceType_i32);
     if (TableIcmp64[Index].IsSigned) {
       Variable *ScratchReg = makeReg(IceType_i32);
       _cmp(Src0Lo, Src1LoRF);
       _sbcs(ScratchReg, Src0Hi, Src1HiRF);
       // ScratchReg isn't going to be used, but we need the
       // side-effect of setting flags from this operation.
@@ skipping 38 matching lines @@
   // We'll go with the LLVM way for now, since it's shorter and has just as
   // few dependencies.
   int32_t ShiftAmt = 32 - getScalarIntBitWidth(Src0->getType());
   assert(ShiftAmt >= 0);
   Constant *ShiftConst = nullptr;
   Variable *Src0R = nullptr;
   Variable *T = makeReg(IceType_i32);
   if (ShiftAmt) {
     ShiftConst = Ctx->getConstantInt32(ShiftAmt);
     Src0R = makeReg(IceType_i32);
-    _lsl(Src0R, legalizeToVar(Src0), ShiftConst);
+    _lsl(Src0R, legalizeToReg(Src0), ShiftConst);
   } else {
-    Src0R = legalizeToVar(Src0);
+    Src0R = legalizeToReg(Src0);
   }
   _mov(T, Zero);
   if (ShiftAmt) {
-    Variable *Src1R = legalizeToVar(Src1);
+    Variable *Src1R = legalizeToReg(Src1);
     OperandARM32FlexReg *Src1RShifted = OperandARM32FlexReg::create(
         Func, IceType_i32, Src1R, OperandARM32::LSL, ShiftConst);
     _cmp(Src0R, Src1RShifted);
   } else {
     Operand *Src1RF = legalize(Src1, Legal_Reg | Legal_Flex);
     _cmp(Src0R, Src1RF);
   }
   _mov_nonkillable(T, One, getIcmp32Mapping(Inst->getCondition()));
   _mov(Dest, T);
   return;
@@ skipping 33 matching lines @@
   case Intrinsics::AtomicStore: {
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   case Intrinsics::Bswap: {
     Variable *Dest = Instr->getDest();
     Operand *Val = Instr->getArg(0);
     Type Ty = Val->getType();
     if (Ty == IceType_i64) {
       Val = legalizeUndef(Val);
-      Variable *Val_Lo = legalizeToVar(loOperand(Val));
-      Variable *Val_Hi = legalizeToVar(hiOperand(Val));
+      Variable *Val_Lo = legalizeToReg(loOperand(Val));
+      Variable *Val_Hi = legalizeToReg(hiOperand(Val));
       Variable *T_Lo = makeReg(IceType_i32);
       Variable *T_Hi = makeReg(IceType_i32);
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       _rev(T_Lo, Val_Lo);
       _rev(T_Hi, Val_Hi);
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
     } else {
       assert(Ty == IceType_i32 || Ty == IceType_i16);
-      Variable *ValR = legalizeToVar(Val);
+      Variable *ValR = legalizeToReg(Val);
       Variable *T = makeReg(Ty);
       _rev(T, ValR);
       if (Val->getType() == IceType_i16) {
         Operand *Sixteen =
             legalize(Ctx->getConstantInt32(16), Legal_Reg | Legal_Flex);
         _lsr(T, T, Sixteen);
       }
       _mov(Dest, T);
     }
     return;
@@ skipping 20 matching lines @@
     return;
   }
   case Intrinsics::Ctlz: {
     // The "is zero undef" parameter is ignored and we always return
     // a well-defined value.
     Operand *Val = Instr->getArg(0);
     Variable *ValLoR;
     Variable *ValHiR = nullptr;
     if (Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
-      ValLoR = legalizeToVar(loOperand(Val));
-      ValHiR = legalizeToVar(hiOperand(Val));
+      ValLoR = legalizeToReg(loOperand(Val));
+      ValHiR = legalizeToReg(hiOperand(Val));
     } else {
-      ValLoR = legalizeToVar(Val);
+      ValLoR = legalizeToReg(Val);
     }
     lowerCLZ(Instr->getDest(), ValLoR, ValHiR);
     return;
   }
   case Intrinsics::Cttz: {
     // Essentially like Clz, but reverse the bits first.
     Operand *Val = Instr->getArg(0);
     Variable *ValLoR;
     Variable *ValHiR = nullptr;
     if (Val->getType() == IceType_i64) {
       Val = legalizeUndef(Val);
-      ValLoR = legalizeToVar(loOperand(Val));
-      ValHiR = legalizeToVar(hiOperand(Val));
+      ValLoR = legalizeToReg(loOperand(Val));
+      ValHiR = legalizeToReg(hiOperand(Val));
       Variable *TLo = makeReg(IceType_i32);
       Variable *THi = makeReg(IceType_i32);
       _rbit(TLo, ValLoR);
       _rbit(THi, ValHiR);
       ValLoR = THi;
       ValHiR = TLo;
     } else {
-      ValLoR = legalizeToVar(Val);
+      ValLoR = legalizeToReg(Val);
       Variable *T = makeReg(IceType_i32);
       _rbit(T, ValLoR);
       ValLoR = T;
     }
     lowerCLZ(Instr->getDest(), ValLoR, ValHiR);
     return;
   }
   case Intrinsics::Fabs: {
     UnimplementedError(Func->getContext()->getFlags());
     return;
@@ skipping 137 matching lines @@
 void TargetARM32::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetARM32::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = Inst->getRetValue();
     if (Src0->getType() == IceType_i64) {
       Src0 = legalizeUndef(Src0);
-      Variable *R0 = legalizeToVar(loOperand(Src0), RegARM32::Reg_r0);
-      Variable *R1 = legalizeToVar(hiOperand(Src0), RegARM32::Reg_r1);
+      Variable *R0 = legalizeToReg(loOperand(Src0), RegARM32::Reg_r0);
+      Variable *R1 = legalizeToReg(hiOperand(Src0), RegARM32::Reg_r1);
       Reg = R0;
       Context.insert(InstFakeUse::create(Func, R1));
     } else if (isScalarFloatingType(Src0->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else if (isVectorType(Src0->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else {
       Operand *Src0F = legalize(Src0, Legal_Reg | Legal_Flex);
       _mov(Reg, Src0F, CondARM32::AL, RegARM32::Reg_r0);
     }
@@ skipping 23 matching lines @@
   if (isVectorType(DestTy)) {
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   if (isFloatingType(DestTy)) {
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   // TODO(jvoung): handle folding opportunities.
   // cmp cond, #0; mov t, SrcF; mov_cond t, SrcT; mov dest, t
-  Variable *CmpOpnd0 = legalizeToVar(Condition);
+  Variable *CmpOpnd0 = legalizeToReg(Condition);
   Operand *CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
   _cmp(CmpOpnd0, CmpOpnd1);
   CondARM32::Cond Cond = CondARM32::NE;
   if (DestTy == IceType_i64) {
     SrcT = legalizeUndef(SrcT);
     SrcF = legalizeUndef(SrcF);
     // Set the low portion.
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *TLo = nullptr;
     Operand *SrcFLo = legalize(loOperand(SrcF), Legal_Reg | Legal_Flex);
@@ skipping 20 matching lines @@
 }
 
 void TargetARM32::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
   Operand *Addr = Inst->getAddr();
   OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
   Type Ty = NewAddr->getType();
 
   if (Ty == IceType_i64) {
     Value = legalizeUndef(Value);
-    Variable *ValueHi = legalizeToVar(hiOperand(Value));
-    Variable *ValueLo = legalizeToVar(loOperand(Value));
+    Variable *ValueHi = legalizeToReg(hiOperand(Value));
+    Variable *ValueLo = legalizeToReg(loOperand(Value));
     _str(ValueHi, llvm::cast<OperandARM32Mem>(hiOperand(NewAddr)));
     _str(ValueLo, llvm::cast<OperandARM32Mem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
     UnimplementedError(Func->getContext()->getFlags());
   } else {
-    Variable *ValueR = legalizeToVar(Value);
+    Variable *ValueR = legalizeToReg(Value);
     _str(ValueR, NewAddr);
   }
 }
 
 void TargetARM32::doAddressOptStore() {
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
   Operand *Src0 = Inst->getComparison();
   SizeT NumCases = Inst->getNumCases();
   if (Src0->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
-    Variable *Src0Lo = legalizeToVar(loOperand(Src0));
-    Variable *Src0Hi = legalizeToVar(hiOperand(Src0));
+    Variable *Src0Lo = legalizeToReg(loOperand(Src0));
+    Variable *Src0Hi = legalizeToReg(hiOperand(Src0));
     for (SizeT I = 0; I < NumCases; ++I) {
       Operand *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
       Operand *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
       ValueLo = legalize(ValueLo, Legal_Reg | Legal_Flex);
       ValueHi = legalize(ValueHi, Legal_Reg | Legal_Flex);
       _cmp(Src0Lo, ValueLo);
       _cmp(Src0Hi, ValueHi, CondARM32::EQ);
       _br(Inst->getLabel(I), CondARM32::EQ);
     }
     _br(Inst->getLabelDefault());
     return;
   }
 
   // 32 bit integer
-  Variable *Src0Var = legalizeToVar(Src0);
+  Variable *Src0Var = legalizeToReg(Src0);
   for (SizeT I = 0; I < NumCases; ++I) {
     Operand *Value = Ctx->getConstantInt32(Inst->getValue(I));
     Value = legalize(Value, Legal_Reg | Legal_Flex);
     _cmp(Src0Var, Value);
     _br(Inst->getLabel(I), CondARM32::EQ);
   }
   _br(Inst->getLabelDefault());
 }
 
 void TargetARM32::lowerUnreachable(const InstUnreachable * /*Inst*/) {
@@ skipping 47 matching lines @@
   // (e.g., OperandARM32Mem and !Legal_Mem), we can always copy
   // to a register.
   if (auto Mem = llvm::dyn_cast<OperandARM32Mem>(From)) {
     // Before doing anything with a Mem operand, we need to ensure
     // that the Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
-      RegBase = legalizeToVar(Base);
+      RegBase = legalizeToReg(Base);
     }
     if (Index) {
-      RegIndex = legalizeToVar(Index);
+      RegIndex = legalizeToReg(Index);
     }
     // Create a new operand if there was a change.
     if (Base != RegBase || Index != RegIndex) {
       // There is only a reg +/- reg or reg + imm form.
       // Figure out which to re-create.
       if (Mem->isRegReg()) {
         Mem = OperandARM32Mem::create(Func, Ty, RegBase, RegIndex,
                                       Mem->getShiftOp(), Mem->getShiftAmt(),
                                       Mem->getAddrMode());
       } else {
@@ skipping 94 matching lines @@
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
 
   return From;
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
-Variable *TargetARM32::legalizeToVar(Operand *From, int32_t RegNum) {
+Variable *TargetARM32::legalizeToReg(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
 Operand *TargetARM32::legalizeUndef(Operand *From, int32_t RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero.  Another option is to lower undefs to an
     // uninitialized register; however, using an uninitialized register
     // results in less predictable code.
@@ skipping 16 matching lines @@
   OperandARM32Mem *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand);
   // It may be the case that address mode optimization already creates
   // an OperandARM32Mem, so in that case it wouldn't need another level
   // of transformation.
   if (Mem) {
     return llvm::cast<OperandARM32Mem>(legalize(Mem));
   }
   // If we didn't do address mode optimization, then we only
   // have a base/offset to work with. ARM always requires a base
   // register, so just use that to hold the operand.
-  Variable *Base = legalizeToVar(Operand);
+  Variable *Base = legalizeToReg(Operand);
   return OperandARM32Mem::create(
       Func, Ty, Base,
       llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32)));
 }
 
 Variable *TargetARM32::makeReg(Type Type, int32_t RegNum) {
   // There aren't any 64-bit integer registers for ARM32.
   assert(Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum == Variable::NoRegister)
@@ skipping 130 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice