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Unified Diff: opcodes/mips-dis.c

Issue 124383005: GDB 7.6.50 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@upstream
Patch Set: Created 6 years, 11 months ago
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Index: opcodes/mips-dis.c
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index c15c6dfedf5f6966b1181421245e49c702a78613..1929ffcac95a7a85c512a5fcc2f5278426e4043a 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -51,100 +51,6 @@ struct mips_cp0sel_name
const char * const name;
};
-/* The mips16 registers. */
-static const unsigned int mips16_to_32_reg_map[] =
-{
- 16, 17, 2, 3, 4, 5, 6, 7
-};
-
-/* The microMIPS registers with type b. */
-#define micromips_to_32_reg_b_map mips16_to_32_reg_map
-
-/* The microMIPS registers with type c. */
-#define micromips_to_32_reg_c_map mips16_to_32_reg_map
-
-/* The microMIPS registers with type d. */
-#define micromips_to_32_reg_d_map mips16_to_32_reg_map
-
-/* The microMIPS registers with type e. */
-#define micromips_to_32_reg_e_map mips16_to_32_reg_map
-
-/* The microMIPS registers with type f. */
-#define micromips_to_32_reg_f_map mips16_to_32_reg_map
-
-/* The microMIPS registers with type g. */
-#define micromips_to_32_reg_g_map mips16_to_32_reg_map
-
-/* The microMIPS registers with type h. */
-static const unsigned int micromips_to_32_reg_h_map[] =
-{
- 5, 5, 6, 4, 4, 4, 4, 4
-};
-
-/* The microMIPS registers with type i. */
-static const unsigned int micromips_to_32_reg_i_map[] =
-{
- 6, 7, 7, 21, 22, 5, 6, 7
-};
-
-/* The microMIPS registers with type j: 32 registers. */
-
-/* The microMIPS registers with type l. */
-#define micromips_to_32_reg_l_map mips16_to_32_reg_map
-
-/* The microMIPS registers with type m. */
-static const unsigned int micromips_to_32_reg_m_map[] =
-{
- 0, 17, 2, 3, 16, 18, 19, 20
-};
-
-/* The microMIPS registers with type n. */
-#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
-
-/* The microMIPS registers with type p: 32 registers. */
-
-/* The microMIPS registers with type q. */
-static const unsigned int micromips_to_32_reg_q_map[] =
-{
- 0, 17, 2, 3, 4, 5, 6, 7
-};
-
-/* reg type s is $29. */
-
-/* reg type t is the same as the last register. */
-
-/* reg type y is $31. */
-
-/* reg type z is $0. */
-
-/* micromips imm B type. */
-static const int micromips_imm_b_map[8] =
-{
- 1, 4, 8, 12, 16, 20, 24, -1
-};
-
-/* micromips imm C type. */
-static const int micromips_imm_c_map[16] =
-{
- 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
-};
-
-/* micromips imm D type: (-512..511)<<1. */
-/* micromips imm E type: (-64..63)<<1. */
-/* micromips imm F type: (0..63). */
-/* micromips imm G type: (-1..14). */
-/* micromips imm H type: (0..15)<<1. */
-/* micromips imm I type: (-1..126). */
-/* micromips imm J type: (0..15)<<2. */
-/* micromips imm L type: (0..15). */
-/* micromips imm M type: (1..8). */
-/* micromips imm W type: (0..63)<<2. */
-/* micromips imm X type: (-8..7). */
-/* micromips imm Y type: (-258..-3, 2..257)<<2. */
-
-#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
-
-
static const char * const mips_gpr_names_numeric[32] =
{
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
@@ -233,6 +139,30 @@ static const char * const mips_cp0_names_r4000[32] =
"c0_taglo", "c0_taghi", "c0_errorepc", "$31",
};
+static const char * const mips_cp0_names_r5900[32] =
+{
+ "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
+ "c0_context", "c0_pagemask", "c0_wired", "$7",
+ "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
+ "c0_sr", "c0_cause", "c0_epc", "c0_prid",
+ "c0_config", "$17", "$18", "$19",
+ "$20", "$21", "$22", "c0_badpaddr",
+ "c0_depc", "c0_perfcnt", "$26", "$27",
+ "c0_taglo", "c0_taghi", "c0_errorepc", "$31"
+};
+
+static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] =
+{
+ { 24, 2, "c0_iab" },
+ { 24, 3, "c0_iabm" },
+ { 24, 4, "c0_dab" },
+ { 24, 5, "c0_dabm" },
+ { 24, 6, "c0_dvb" },
+ { 24, 7, "c0_dvbm" },
+ { 25, 1, "c0_perfcnt,1" },
+ { 25, 2, "c0_perfcnt,2" }
+};
+
static const char * const mips_cp0_names_mips3264[32] =
{
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
@@ -471,6 +401,15 @@ static const char * const mips_hwr_names_mips3264r2[32] =
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
+static const char * const msa_control_names[32] =
+{
+ "msa_ir", "msa_csr", "msa_access", "msa_save",
+ "msa_modify", "msa_request", "msa_map", "msa_unmap",
+ "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
+ "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
+ "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
+};
+
struct mips_abi_choice
{
const char * name;
@@ -493,6 +432,7 @@ struct mips_arch_choice
unsigned long bfd_mach;
int processor;
int isa;
+ int ase;
const char * const *cp0_names;
const struct mips_cp0sel_name *cp0sel_names;
unsigned int cp0sel_names_len;
@@ -501,54 +441,56 @@ struct mips_arch_choice
const struct mips_arch_choice mips_arch_choices[] =
{
- { "numeric", 0, 0, 0, 0,
+ { "numeric", 0, 0, 0, 0, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
+ { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
- { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
+ { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
+ { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
- { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
+ { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
+ { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
+ { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
+ { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
+ { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
+ { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
- { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
+ { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
+ { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
+ { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
+ { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
+ { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
+ { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
+ mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
+ { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
+ { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
+ { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
+ { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
+ { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
+ { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
+ { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
+ { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
- { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
+ { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
@@ -557,64 +499,66 @@ const struct mips_arch_choice mips_arch_choices[] =
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
- ISA_MIPS32 | INSN_SMARTMIPS,
+ ISA_MIPS32, ASE_SMARTMIPS,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
- (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
- | INSN_MIPS3D | INSN_MT | INSN_MCU),
+ ISA_MIPS32R2,
+ (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
- ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
+ ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
- (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
- | INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU),
+ ISA_MIPS64R2,
+ (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
{ "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
- ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
+ ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
mips_cp0_names_sb1,
mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
mips_hwr_names_numeric },
{ "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
- ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
+ ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
- ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
+ ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
- ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
+ ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
- ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
+ ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
mips_hwr_names_numeric },
{ "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
- ISA_MIPS64R2 | INSN_OCTEONP, mips_cp0_names_numeric,
+ ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
- ISA_MIPS64R2 | INSN_OCTEON2, mips_cp0_names_numeric,
+ ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
- ISA_MIPS64 | INSN_XLR,
+ ISA_MIPS64 | INSN_XLR, 0,
mips_cp0_names_xlr,
mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
mips_hwr_names_numeric },
@@ -622,14 +566,14 @@ const struct mips_arch_choice mips_arch_choices[] =
/* XLP is mostly like XLR, with the prominent exception it is being
MIPS64R2. */
{ "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
- ISA_MIPS64R2 | INSN_XLR,
+ ISA_MIPS64R2 | INSN_XLR, 0,
mips_cp0_names_xlr,
mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
mips_hwr_names_numeric },
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
- { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
+ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
};
@@ -638,6 +582,7 @@ const struct mips_arch_choice mips_arch_choices[] =
values. */
static int mips_processor;
static int mips_isa;
+static int mips_ase;
static int micromips_ase;
static const char * const *mips_gpr_names;
static const char * const *mips_fpr_names;
@@ -743,6 +688,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
mips_isa = ISA_MIPS3;
mips_processor = CPU_R3000;
micromips_ase = 0;
+ mips_ase = 0;
mips_gpr_names = mips_gpr_names_oldabi;
mips_fpr_names = mips_fpr_names_numeric;
mips_cp0_names = mips_cp0_names_numeric;
@@ -770,12 +716,14 @@ set_default_mips_dis_options (struct disassemble_info *info)
FIXME: Where does mips_target_info come from? */
target_processor = mips_target_info.processor;
mips_isa = mips_target_info.isa;
+ mips_ase = mips_target_info.ase;
#else
chosen_arch = choose_arch_by_number (info->mach);
if (chosen_arch != NULL)
{
mips_processor = chosen_arch->processor;
mips_isa = chosen_arch->isa;
+ mips_ase = chosen_arch->ase;
mips_cp0_names = chosen_arch->cp0_names;
mips_cp0sel_names = chosen_arch->cp0sel_names;
mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
@@ -798,6 +746,22 @@ parse_mips_dis_option (const char *option, unsigned int len)
no_aliases = 1;
return;
}
+
+ if (CONST_STRNEQ (option, "msa"))
+ {
+ mips_ase |= ASE_MSA;
+ if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2)
+ mips_ase |= ASE_MSA64;
+ return;
+ }
+
+ if (CONST_STRNEQ (option, "virt"))
+ {
+ mips_ase |= ASE_VIRT;
+ if (mips_isa & ISA_MIPS64R2)
+ mips_ase |= ASE_VIRT64;
+ return;
+ }
/* Look for the = that delimits the end of the option name. */
for (i = 0; i < len; i++)
@@ -925,581 +889,481 @@ lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
return &names[i];
return NULL;
}
-
-/* Print insn arguments for 32/64-bit code. */
+
+/* Print register REGNO, of type TYPE, for instruction OPCODE. */
static void
-print_insn_args (const char *d,
- register unsigned long int l,
- bfd_vma pc,
- struct disassemble_info *info,
- const struct mips_opcode *opp)
+print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
+ enum mips_reg_operand_type type, int regno)
{
- int op, delta;
- unsigned int lsb, msb, msbd;
+ switch (type)
+ {
+ case OP_REG_GP:
+ info->fprintf_func (info->stream, "%s", mips_gpr_names[regno]);
+ break;
- lsb = 0;
+ case OP_REG_FP:
+ info->fprintf_func (info->stream, "%s", mips_fpr_names[regno]);
+ break;
- for (; *d != '\0'; d++)
- {
- switch (*d)
- {
- case ',':
- case '(':
- case ')':
- case '[':
- case ']':
- (*info->fprintf_func) (info->stream, "%c", *d);
- break;
+ case OP_REG_CCC:
+ if (opcode->pinfo & (FP_D | FP_S))
+ info->fprintf_func (info->stream, "$fcc%d", regno);
+ else
+ info->fprintf_func (info->stream, "$cc%d", regno);
+ break;
- case '+':
- /* Extension character; switch for second char. */
- d++;
- switch (*d)
- {
- case '\0':
- /* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, incomplete extension sequence (+)"));
- return;
+ case OP_REG_VEC:
+ if (opcode->membership & INSN_5400)
+ info->fprintf_func (info->stream, "$f%d", regno);
+ else
+ info->fprintf_func (info->stream, "$v%d", regno);
+ break;
- case 'A':
- lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
- break;
-
- case 'B':
- msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
- break;
-
- case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI1) & OP_MASK_UDI1);
- break;
-
- case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI2) & OP_MASK_UDI2);
- break;
-
- case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI3) & OP_MASK_UDI3);
- break;
-
- case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_UDI4) & OP_MASK_UDI4);
- break;
-
- case 'C':
- case 'H':
- msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
- break;
-
- case 'D':
- {
- const struct mips_cp0sel_name *n;
- unsigned int cp0reg, sel;
-
- cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
-
- /* CP0 register including 'sel' code for mtcN (et al.), to be
- printed textually if known. If not known, print both
- CP0 register name and sel numerically since CP0 register
- with sel 0 may have a name unrelated to register being
- printed. */
- n = lookup_mips_cp0sel_name(mips_cp0sel_names,
- mips_cp0sel_names_len, cp0reg, sel);
- if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
- else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
- break;
- }
+ case OP_REG_ACC:
+ info->fprintf_func (info->stream, "$ac%d", regno);
+ break;
- case 'E':
- lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", lsb);
- break;
-
- case 'F':
- msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
- break;
-
- case 'G':
- msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
- (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
- break;
-
- case 't': /* Coprocessor 0 reg name */
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RT) &
- OP_MASK_RT]);
- break;
-
- case 'T': /* Coprocessor 0 reg name */
- {
- const struct mips_cp0sel_name *n;
- unsigned int cp0reg, sel;
-
- cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
- sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
-
- /* CP0 register including 'sel' code for mftc0, to be
- printed textually if known. If not known, print both
- CP0 register name and sel numerically since CP0 register
- with sel 0 may have a name unrelated to register being
- printed. */
- n = lookup_mips_cp0sel_name(mips_cp0sel_names,
- mips_cp0sel_names_len, cp0reg, sel);
- if (n != NULL)
- (*info->fprintf_func) (info->stream, "%s", n->name);
- else
- (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
- break;
- }
+ case OP_REG_COPRO:
+ if (opcode->name[strlen (opcode->name) - 1] == '0')
+ info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
+ else
+ info->fprintf_func (info->stream, "$%d", regno);
+ break;
- case 'x': /* bbit bit index */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
- break;
-
- case 'p': /* cins, cins32, exts and exts32 position */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
- break;
-
- case 's': /* cins and exts length-minus-one */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
- break;
-
- case 'S': /* cins32 and exts32 length-minus-one field */
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
- break;
-
- case 'Q': /* seqi/snei immediate field */
- op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
- /* Sign-extend it. */
- op = (op ^ 512) - 512;
- (*info->fprintf_func) (info->stream, "%d", op);
- break;
-
- case 'a': /* 8-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_A;
- (*info->fprintf_func) (info->stream, "%d", delta);
- break;
-
- case 'b': /* 8-bit signed offset in bit 3 */
- delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B;
- if (delta & 0x80)
- delta |= ~OP_MASK_OFFSET_B;
- (*info->fprintf_func) (info->stream, "%d", delta);
- break;
-
- case 'c': /* 9-bit signed offset in bit 6 */
- delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C;
- if (delta & 0x100)
- delta |= ~OP_MASK_OFFSET_C;
- /* Left shift 4 bits to print the real offset. */
- (*info->fprintf_func) (info->stream, "%d", delta << 4);
- break;
-
- case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]);
- break;
-
- case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]);
- break;
-
- default:
- /* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined extension sequence (+%c)"),
- *d);
- return;
- }
- break;
+ case OP_REG_HW:
+ info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]);
+ break;
- case '2':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_BP) & OP_MASK_BP);
- break;
+ case OP_REG_VF:
+ info->fprintf_func (info->stream, "$vf%d", regno);
+ break;
- case '3':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA3) & OP_MASK_SA3);
- break;
+ case OP_REG_VI:
+ info->fprintf_func (info->stream, "$vi%d", regno);
+ break;
- case '4':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SA4) & OP_MASK_SA4);
- break;
+ case OP_REG_R5900_I:
+ info->fprintf_func (info->stream, "$I");
+ break;
- case '5':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMM8) & OP_MASK_IMM8);
- break;
+ case OP_REG_R5900_Q:
+ info->fprintf_func (info->stream, "$Q");
+ break;
- case '6':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RS) & OP_MASK_RS);
- break;
+ case OP_REG_R5900_R:
+ info->fprintf_func (info->stream, "$R");
+ break;
- case '7':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
- break;
+ case OP_REG_R5900_ACC:
+ info->fprintf_func (info->stream, "$ACC");
+ break;
- case '8':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
- break;
+ case OP_REG_MSA:
+ info->fprintf_func (info->stream, "$w%d", regno);
+ break;
- case '9':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
- break;
+ case OP_REG_MSA_CTRL:
+ info->fprintf_func (info->stream, "%s", msa_control_names[regno]);
+ break;
- case '0': /* dsp 6-bit signed immediate in bit 20 */
- delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
- if (delta & 0x20) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT;
- (*info->fprintf_func) (info->stream, "%d", delta);
- break;
+ }
+}
+
+/* Used to track the state carried over from previous operands in
+ an instruction. */
+struct mips_print_arg_state {
+ /* The value of the last OP_INT seen. We only use this for OP_MSB,
+ where the value is known to be unsigned and small. */
+ unsigned int last_int;
+
+ /* The type and number of the last OP_REG seen. We only use this for
+ OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */
+ enum mips_reg_operand_type last_reg_type;
+ unsigned int last_regno;
+};
- case ':': /* dsp 7-bit signed immediate in bit 19 */
- delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
- if (delta & 0x40) /* test sign bit */
- delta |= ~OP_MASK_DSPSFT_7;
- (*info->fprintf_func) (info->stream, "%d", delta);
- break;
+/* Initialize STATE for the start of an instruction. */
- case '~':
- delta = (l >> OP_SH_OFFSET12) & OP_MASK_OFFSET12;
- if (delta & 0x800)
- delta |= ~0x7ff;
- (*info->fprintf_func) (info->stream, "%d", delta);
- break;
+static inline void
+init_print_arg_state (struct mips_print_arg_state *state)
+{
+ memset (state, 0, sizeof (*state));
+}
- case '\\':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_3BITPOS) & OP_MASK_3BITPOS);
- break;
+/* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND,
+ whose value is given by UVAL. */
- case '\'':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
- break;
+static void
+print_vu0_channel (struct disassemble_info *info,
+ const struct mips_operand *operand, unsigned int uval)
+{
+ if (operand->size == 4)
+ info->fprintf_func (info->stream, "%s%s%s%s",
+ uval & 8 ? "x" : "",
+ uval & 4 ? "y" : "",
+ uval & 2 ? "z" : "",
+ uval & 1 ? "w" : "");
+ else if (operand->size == 2)
+ info->fprintf_func (info->stream, "%c", "xyzw"[uval]);
+ else
+ abort ();
+}
- case '@': /* dsp 10-bit signed immediate in bit 16 */
- delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
- if (delta & 0x200) /* test sign bit */
- delta |= ~OP_MASK_IMM10;
- (*info->fprintf_func) (info->stream, "%d", delta);
- break;
+/* Print operand OPERAND of OPCODE, using STATE to track inter-operand state.
+ UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is
+ the base address for OP_PCREL operands. */
- case '!':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_U) & OP_MASK_MT_U);
- break;
+static void
+print_insn_arg (struct disassemble_info *info,
+ struct mips_print_arg_state *state,
+ const struct mips_opcode *opcode,
+ const struct mips_operand *operand,
+ bfd_vma base_pc,
+ unsigned int uval)
+{
+ const fprintf_ftype infprintf = info->fprintf_func;
+ void *is = info->stream;
- case '$':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_MT_H) & OP_MASK_MT_H);
- break;
+ switch (operand->type)
+ {
+ case OP_INT:
+ {
+ const struct mips_int_operand *int_op;
- case '*':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
- break;
+ int_op = (const struct mips_int_operand *) operand;
+ uval = mips_decode_int_operand (int_op, uval);
+ state->last_int = uval;
+ if (int_op->print_hex)
+ infprintf (is, "0x%x", uval);
+ else
+ infprintf (is, "%d", uval);
+ }
+ break;
- case '&':
- (*info->fprintf_func) (info->stream, "$ac%ld",
- (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
- break;
+ case OP_MAPPED_INT:
+ {
+ const struct mips_mapped_int_operand *mint_op;
- case 'g':
- /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
- break;
+ mint_op = (const struct mips_mapped_int_operand *) operand;
+ uval = mint_op->int_map[uval];
+ state->last_int = uval;
+ if (mint_op->print_hex)
+ infprintf (is, "0x%x", uval);
+ else
+ infprintf (is, "%d", uval);
+ }
+ break;
- case 's':
- case 'b':
- case 'r':
- case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
- break;
+ case OP_MSB:
+ {
+ const struct mips_msb_operand *msb_op;
- case 't':
- case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
- break;
+ msb_op = (const struct mips_msb_operand *) operand;
+ uval += msb_op->bias;
+ if (msb_op->add_lsb)
+ uval -= state->last_int;
+ infprintf (is, "0x%x", uval);
+ }
+ break;
- case 'i':
- case 'u':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
- break;
+ case OP_REG:
+ case OP_OPTIONAL_REG:
+ {
+ const struct mips_reg_operand *reg_op;
- case 'j': /* Same as i, but sign-extended. */
- case 'o':
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- (*info->fprintf_func) (info->stream, "%d",
- delta);
- break;
+ reg_op = (const struct mips_reg_operand *) operand;
+ uval = mips_decode_reg_operand (reg_op, uval);
+ print_reg (info, opcode, reg_op->reg_type, uval);
- case 'h':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_PREFX)
- & OP_MASK_PREFX));
- break;
+ state->last_reg_type = reg_op->reg_type;
+ state->last_regno = uval;
+ }
+ break;
- case 'k':
- (*info->fprintf_func) (info->stream, "0x%x",
- (unsigned int) ((l >> OP_SH_CACHE)
- & OP_MASK_CACHE));
- break;
+ case OP_REG_PAIR:
+ {
+ const struct mips_reg_pair_operand *pair_op;
+
+ pair_op = (const struct mips_reg_pair_operand *) operand;
+ print_reg (info, opcode, pair_op->reg_type,
+ pair_op->reg1_map[uval]);
+ infprintf (is, ",");
+ print_reg (info, opcode, pair_op->reg_type,
+ pair_op->reg2_map[uval]);
+ }
+ break;
- case 'a':
- info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
- | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
- /* For gdb disassembler, force odd address on jalx. */
- if (info->flavour == bfd_target_unknown_flavour
- && strcmp (opp->name, "jalx") == 0)
- info->target |= 1;
- (*info->print_address_func) (info->target, info);
- break;
+ case OP_PCREL:
+ {
+ const struct mips_pcrel_operand *pcrel_op;
- case 'p':
- /* Sign extend the displacement. */
- delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
- if (delta & 0x8000)
- delta |= ~0xffff;
- info->target = (delta << 2) + pc + INSNLEN;
- (*info->print_address_func) (info->target, info);
- break;
+ pcrel_op = (const struct mips_pcrel_operand *) operand;
+ info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval);
- case 'd':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
- break;
+ /* Preserve the ISA bit for the GDB disassembler,
+ otherwise clear it. */
+ if (info->flavour != bfd_target_unknown_flavour)
+ info->target &= -2;
- case 'U':
- {
- /* First check for both rd and rt being equal. */
- unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
- if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
- else
- {
- /* If one is zero use the other. */
- if (reg == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
- else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[reg]);
- else /* Bogus, result depends on processor. */
- (*info->fprintf_func) (info->stream, "%s or %s",
- mips_gpr_names[reg],
- mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
- }
- }
- break;
+ (*info->print_address_func) (info->target, info);
+ }
+ break;
- case 'z':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
- break;
+ case OP_PERF_REG:
+ infprintf (is, "%d", uval);
+ break;
- case '<':
- case '1':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
- break;
+ case OP_ADDIUSP_INT:
+ {
+ int sval;
- case 'c':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE) & OP_MASK_CODE);
- break;
+ sval = mips_signed_operand (operand, uval) * 4;
+ if (sval >= -8 && sval < 8)
+ sval ^= 0x400;
+ infprintf (is, "%d", sval);
+ break;
+ }
- case 'q':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE2) & OP_MASK_CODE2);
- break;
+ case OP_CLO_CLZ_DEST:
+ {
+ unsigned int reg1, reg2;
+
+ reg1 = uval & 31;
+ reg2 = uval >> 5;
+ /* If one is zero use the other. */
+ if (reg1 == reg2 || reg2 == 0)
+ infprintf (is, "%s", mips_gpr_names[reg1]);
+ else if (reg1 == 0)
+ infprintf (is, "%s", mips_gpr_names[reg2]);
+ else
+ /* Bogus, result depends on processor. */
+ infprintf (is, "%s or %s", mips_gpr_names[reg1],
+ mips_gpr_names[reg2]);
+ }
+ break;
- case 'C':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_COPZ) & OP_MASK_COPZ);
- break;
+ case OP_LWM_SWM_LIST:
+ if (operand->size == 2)
+ {
+ if (uval == 0)
+ infprintf (is, "%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[31]);
+ else
+ infprintf (is, "%s-%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[16 + uval],
+ mips_gpr_names[31]);
+ }
+ else
+ {
+ int s_reg_encode;
- case 'B':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE20) & OP_MASK_CODE20);
- break;
+ s_reg_encode = uval & 0xf;
+ if (s_reg_encode != 0)
+ {
+ if (s_reg_encode == 1)
+ infprintf (is, "%s", mips_gpr_names[16]);
+ else if (s_reg_encode < 9)
+ infprintf (is, "%s-%s",
+ mips_gpr_names[16],
+ mips_gpr_names[15 + s_reg_encode]);
+ else if (s_reg_encode == 9)
+ infprintf (is, "%s-%s,%s",
+ mips_gpr_names[16],
+ mips_gpr_names[23],
+ mips_gpr_names[30]);
+ else
+ infprintf (is, "UNKNOWN");
+ }
- case 'J':
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_CODE19) & OP_MASK_CODE19);
- break;
+ if (uval & 0x10) /* For ra. */
+ {
+ if (s_reg_encode == 0)
+ infprintf (is, "%s", mips_gpr_names[31]);
+ else
+ infprintf (is, ",%s", mips_gpr_names[31]);
+ }
+ }
+ break;
- case 'S':
- case 'V':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
- break;
+ case OP_ENTRY_EXIT_LIST:
+ {
+ const char *sep;
+ unsigned int amask, smask;
- case 'T':
- case 'W':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
- break;
+ sep = "";
+ amask = (uval >> 3) & 7;
+ if (amask > 0 && amask < 5)
+ {
+ infprintf (is, "%s", mips_gpr_names[4]);
+ if (amask > 1)
+ infprintf (is, "-%s", mips_gpr_names[amask + 3]);
+ sep = ",";
+ }
- case 'D':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
- break;
+ smask = (uval >> 1) & 3;
+ if (smask == 3)
+ {
+ infprintf (is, "%s??", sep);
+ sep = ",";
+ }
+ else if (smask > 0)
+ {
+ infprintf (is, "%s%s", sep, mips_gpr_names[16]);
+ if (smask > 1)
+ infprintf (is, "-%s", mips_gpr_names[smask + 15]);
+ sep = ",";
+ }
- case 'R':
- (*info->fprintf_func) (info->stream, "%s",
- mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
- break;
+ if (uval & 1)
+ {
+ infprintf (is, "%s%s", sep, mips_gpr_names[31]);
+ sep = ",";
+ }
- case 'E':
- /* Coprocessor register for lwcN instructions, et al.
+ if (amask == 5 || amask == 6)
+ {
+ infprintf (is, "%s%s", sep, mips_fpr_names[0]);
+ if (amask == 6)
+ infprintf (is, "-%s", mips_fpr_names[1]);
+ }
+ }
+ break;
- Note that there is no load/store cp0 instructions, and
- that FPU (cp1) instructions disassemble this field using
- 'T' format. Therefore, until we gain understanding of
- cp2 register names, we can simply print the register
- numbers. */
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RT) & OP_MASK_RT);
- break;
+ case OP_SAVE_RESTORE_LIST:
+ /* Should be handled by the caller due to extend behavior. */
+ abort ();
- case 'G':
- /* Coprocessor register for mtcN instructions, et al. Note
- that FPU (cp1) instructions disassemble this field using
- 'S' format. Therefore, we only need to worry about cp0,
- cp2, and cp3. */
- op = (l >> OP_SH_OP) & OP_MASK_OP;
- if (op == OP_OP_COP0)
- (*info->fprintf_func) (info->stream, "%s",
- mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
- else
- (*info->fprintf_func) (info->stream, "$%ld",
- (l >> OP_SH_RD) & OP_MASK_RD);
- break;
+ case OP_MDMX_IMM_REG:
+ {
+ unsigned int vsel;
- case 'K':
- (*info->fprintf_func) (info->stream, "%s",
- mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
- break;
+ vsel = uval >> 5;
+ uval &= 31;
+ if ((vsel & 0x10) == 0)
+ {
+ int fmt;
- case 'N':
- (*info->fprintf_func) (info->stream,
- ((opp->pinfo & (FP_D | FP_S)) != 0
- ? "$fcc%ld" : "$cc%ld"),
- (l >> OP_SH_BCC) & OP_MASK_BCC);
- break;
+ vsel &= 0x0f;
+ for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
+ if ((vsel & 1) == 0)
+ break;
+ print_reg (info, opcode, OP_REG_VEC, uval);
+ infprintf (is, "[%d]", vsel >> 1);
+ }
+ else if ((vsel & 0x08) == 0)
+ print_reg (info, opcode, OP_REG_VEC, uval);
+ else
+ infprintf (is, "0x%x", uval);
+ }
+ break;
- case 'M':
- (*info->fprintf_func) (info->stream, "$fcc%ld",
- (l >> OP_SH_CCC) & OP_MASK_CCC);
- break;
+ case OP_REPEAT_PREV_REG:
+ print_reg (info, opcode, state->last_reg_type, state->last_regno);
+ break;
- case 'P':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
- break;
+ case OP_REPEAT_DEST_REG:
+ /* Should always match OP_REPEAT_PREV_REG first. */
+ abort ();
- case 'e':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
- break;
+ case OP_PC:
+ infprintf (is, "$pc");
+ break;
- case '%':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
- break;
+ case OP_VU0_SUFFIX:
+ case OP_VU0_MATCH_SUFFIX:
+ print_vu0_channel (info, operand, uval);
+ break;
- case 'H':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_SEL) & OP_MASK_SEL);
- break;
+ case OP_IMM_INDEX:
+ infprintf (is, "[%d]", uval);
+ break;
- case 'O':
- (*info->fprintf_func) (info->stream, "%ld",
- (l >> OP_SH_ALN) & OP_MASK_ALN);
- break;
+ case OP_REG_INDEX:
+ infprintf (is, "[");
+ print_reg (info, opcode, OP_REG_GP, uval);
+ infprintf (is, "]");
+ break;
+ }
+}
- case 'Q':
- {
- unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
+/* Print the arguments for INSN, which is described by OPCODE.
+ Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC
+ as the base of OP_PCREL operands. */
- if ((vsel & 0x10) == 0)
- {
- int fmt;
-
- vsel &= 0x0f;
- for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
- if ((vsel & 1) == 0)
- break;
- (*info->fprintf_func) (info->stream, "$v%ld[%d]",
- (l >> OP_SH_FT) & OP_MASK_FT,
- vsel >> 1);
- }
- else if ((vsel & 0x08) == 0)
- {
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
- }
- else
- {
- (*info->fprintf_func) (info->stream, "0x%lx",
- (l >> OP_SH_FT) & OP_MASK_FT);
- }
- }
- break;
-
- case 'X':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FD) & OP_MASK_FD);
- break;
+static void
+print_insn_args (struct disassemble_info *info,
+ const struct mips_opcode *opcode,
+ const struct mips_operand *(*decode_operand) (const char *),
+ unsigned int insn, bfd_vma base_pc)
+{
+ const fprintf_ftype infprintf = info->fprintf_func;
+ void *is = info->stream;
+ struct mips_print_arg_state state;
+ const struct mips_operand *operand;
+ const char *s;
- case 'Y':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FS) & OP_MASK_FS);
+ init_print_arg_state (&state);
+ for (s = opcode->args; *s; ++s)
+ {
+ switch (*s)
+ {
+ case ',':
+ case '(':
+ case ')':
+ infprintf (is, "%c", *s);
break;
- case 'Z':
- (*info->fprintf_func) (info->stream, "$v%ld",
- (l >> OP_SH_FT) & OP_MASK_FT);
+ case '#':
+ ++s;
+ infprintf (is, "%c%c", *s, *s);
break;
default:
- /* xgettext:c-format */
- (*info->fprintf_func) (info->stream,
- _("# internal error, undefined modifier (%c)"),
- *d);
- return;
+ operand = decode_operand (s);
+ if (!operand)
+ {
+ /* xgettext:c-format */
+ infprintf (is,
+ _("# internal error, undefined operand in `%s %s'"),
+ opcode->name, opcode->args);
+ return;
+ }
+ if (operand->type == OP_REG
+ && s[1] == ','
+ && s[2] == 'H'
+ && opcode->name[strlen (opcode->name) - 1] == '0')
+ {
+ /* Coprocessor register 0 with sel field (MT ASE). */
+ const struct mips_cp0sel_name *n;
+ unsigned int reg, sel;
+
+ reg = mips_extract_operand (operand, insn);
+ s += 2;
+ operand = decode_operand (s);
+ sel = mips_extract_operand (operand, insn);
+
+ /* CP0 register including 'sel' code for mftc0, to be
+ printed textually if known. If not known, print both
+ CP0 register name and sel numerically since CP0 register
+ with sel 0 may have a name unrelated to register being
+ printed. */
+ n = lookup_mips_cp0sel_name (mips_cp0sel_names,
+ mips_cp0sel_names_len,
+ reg, sel);
+ if (n != NULL)
+ infprintf (is, "%s", n->name);
+ else
+ infprintf (is, "$%d,%d", reg, sel);
+ }
+ else
+ print_insn_arg (info, &state, opcode, operand, base_pc,
+ mips_extract_operand (operand, insn));
+ if (*s == 'm' || *s == '+')
+ ++s;
+ break;
}
}
}
@@ -1511,12 +1375,16 @@ print_insn_args (const char *d,
static int
print_insn_mips (bfd_vma memaddr,
- unsigned long int word,
+ int word,
struct disassemble_info *info)
{
+#define GET_OP(insn, field) \
+ (((insn) >> OP_SH_##field) & OP_MASK_##field)
+ static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ const fprintf_ftype infprintf = info->fprintf_func;
const struct mips_opcode *op;
static bfd_boolean init = 0;
- static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
+ void *is = info->stream;
/* Build a hash table to shorten the search time. */
if (! init)
@@ -1530,7 +1398,7 @@ print_insn_mips (bfd_vma memaddr,
if (op->pinfo == INSN_MACRO
|| (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
continue;
- if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
+ if (i == GET_OP (op->match, OP))
{
mips_hash[i] = op;
break;
@@ -1550,7 +1418,7 @@ print_insn_mips (bfd_vma memaddr,
info->target = 0;
info->target2 = 0;
- op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
+ op = mips_hash[GET_OP (word, OP)];
if (op != NULL)
{
for (; op < &mips_opcodes[NUMOPCODES]; op++)
@@ -1559,18 +1427,15 @@ print_insn_mips (bfd_vma memaddr,
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
&& (word & op->mask) == op->match)
{
- const char *d;
-
/* We always allow to disassemble the jalx instruction. */
- if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
+ if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
&& strcmp (op->name, "jalx"))
continue;
/* Figure out instruction type and branch delay information. */
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
{
- if ((op->pinfo & (INSN_WRITE_GPR_31
- | INSN_WRITE_GPR_D)) != 0)
+ if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0)
info->insn_type = dis_jsr;
else
info->insn_type = dis_branch;
@@ -1586,525 +1451,236 @@ print_insn_mips (bfd_vma memaddr,
info->branch_delay_insns = 1;
}
else if ((op->pinfo & (INSN_STORE_MEMORY
- | INSN_LOAD_MEMORY_DELAY)) != 0)
+ | INSN_LOAD_MEMORY)) != 0)
info->insn_type = dis_dref;
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
+ if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
+ {
+ unsigned int uval;
+
+ infprintf (is, ".");
+ uval = mips_extract_operand (&mips_vu0_channel_mask, word);
+ print_vu0_channel (info, &mips_vu0_channel_mask, uval);
+ }
- d = op->args;
- if (d != NULL && *d != '\0')
+ if (op->args[0])
{
- (*info->fprintf_func) (info->stream, "\t");
- print_insn_args (d, word, memaddr, info, op);
+ infprintf (is, "\t");
+ print_insn_args (info, op, decode_mips_operand, word,
+ memaddr + 4);
}
return INSNLEN;
}
}
}
+#undef GET_OP
/* Handle undefined instructions. */
info->insn_type = dis_noninsn;
- (*info->fprintf_func) (info->stream, "0x%lx", word);
+ infprintf (is, "0x%x", word);
return INSNLEN;
}
/* Disassemble an operand for a mips16 instruction. */
static void
-print_mips16_insn_arg (char type,
- const struct mips_opcode *op,
- int l,
- bfd_boolean use_extend,
- int extend,
- bfd_vma memaddr,
- struct disassemble_info *info)
+print_mips16_insn_arg (struct disassemble_info *info,
+ struct mips_print_arg_state *state,
+ const struct mips_opcode *opcode,
+ char type, bfd_vma memaddr,
+ unsigned insn, bfd_boolean use_extend,
+ unsigned extend, bfd_boolean is_offset)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
+ void *is = info->stream;
+ const struct mips_operand *operand, *ext_operand;
+ unsigned int uval;
+ bfd_vma baseaddr;
+
+ if (!use_extend)
+ extend = 0;
+
switch (type)
{
case ',':
case '(':
case ')':
- (*info->fprintf_func) (info->stream, "%c", type);
+ infprintf (is, "%c", type);
break;
- case 'y':
- case 'w':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RY)
- & MIPS16OP_MASK_RY)));
- break;
-
- case 'x':
- case 'v':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RX)
- & MIPS16OP_MASK_RX)));
- break;
-
- case 'z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_RZ)
- & MIPS16OP_MASK_RZ)));
- break;
-
- case 'Z':
- (*info->fprintf_func) (info->stream, "%s",
- mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
- & MIPS16OP_MASK_MOVE32Z)));
- break;
-
- case '0':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
- break;
-
- case 'S':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
- break;
-
- case 'P':
- (*info->fprintf_func) (info->stream, "$pc");
- break;
+ default:
+ operand = decode_mips16_operand (type, FALSE);
+ if (!operand)
+ {
+ /* xgettext:c-format */
+ infprintf (is, _("# internal error, undefined operand in `%s %s'"),
+ opcode->name, opcode->args);
+ return;
+ }
- case 'R':
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
- break;
+ if (operand->type == OP_SAVE_RESTORE_LIST)
+ {
+ /* Handle this case here because of the complex interation
+ with the EXTEND opcode. */
+ unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j;
+ const char *sep;
- case 'X':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
- & MIPS16OP_MASK_REGR32)]);
- break;
+ amask = extend & 0xf;
+ if (amask == MIPS16_ALL_ARGS)
+ {
+ nargs = 4;
+ nstatics = 0;
+ }
+ else if (amask == MIPS16_ALL_STATICS)
+ {
+ nargs = 0;
+ nstatics = 4;
+ }
+ else
+ {
+ nargs = amask >> 2;
+ nstatics = amask & 3;
+ }
- case 'Y':
- (*info->fprintf_func) (info->stream, "%s",
- mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
- break;
+ sep = "";
+ if (nargs > 0)
+ {
+ infprintf (is, "%s", mips_gpr_names[4]);
+ if (nargs > 1)
+ infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]);
+ sep = ",";
+ }
- case '<':
- case '>':
- case '[':
- case ']':
- case '4':
- case '5':
- case 'H':
- case 'W':
- case 'D':
- case 'j':
- case '6':
- case '8':
- case 'V':
- case 'C':
- case 'U':
- case 'k':
- case 'K':
- case 'p':
- case 'q':
- case 'A':
- case 'B':
- case 'E':
- {
- int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
-
- shift = 0;
- signedp = 0;
- extbits = 16;
- pcrel = 0;
- extu = 0;
- branch = 0;
- switch (type)
- {
- case '<':
- nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
- extbits = 5;
- extu = 1;
- break;
- case '>':
- nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
- extbits = 5;
- extu = 1;
- break;
- case '[':
- nbits = 3;
- immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
- extbits = 6;
- extu = 1;
- break;
- case ']':
- nbits = 3;
- immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
- extbits = 6;
- extu = 1;
- break;
- case '4':
- nbits = 4;
- immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
- signedp = 1;
- extbits = 15;
- break;
- case '5':
- nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
- info->insn_type = dis_dref;
- info->data_size = 1;
- break;
- case 'H':
- nbits = 5;
- shift = 1;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
- info->insn_type = dis_dref;
- info->data_size = 2;
- break;
- case 'W':
- nbits = 5;
- shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
- if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
- && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
+ frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8;
+ if (frame_size == 0 && !use_extend)
+ frame_size = 128;
+ infprintf (is, "%s%d", sep, frame_size);
+
+ if (insn & 0x40) /* $ra */
+ infprintf (is, ",%s", mips_gpr_names[31]);
+
+ nsreg = (extend >> 8) & 0x7;
+ smask = 0;
+ if (insn & 0x20) /* $s0 */
+ smask |= 1 << 0;
+ if (insn & 0x10) /* $s1 */
+ smask |= 1 << 1;
+ if (nsreg > 0) /* $s2-$s8 */
+ smask |= ((1 << nsreg) - 1) << 2;
+
+ for (i = 0; i < 9; i++)
+ if (smask & (1 << i))
{
- info->insn_type = dis_dref;
- info->data_size = 4;
+ infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
+ /* Skip over string of set bits. */
+ for (j = i; smask & (2 << j); j++)
+ continue;
+ if (j > i)
+ infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
+ i = j + 1;
}
- break;
- case 'D':
- nbits = 5;
- shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
- info->insn_type = dis_dref;
- info->data_size = 8;
- break;
- case 'j':
- nbits = 5;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
- signedp = 1;
- break;
- case '6':
- nbits = 6;
- immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
- break;
- case '8':
- nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- break;
- case 'V':
- nbits = 8;
- shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- /* FIXME: This might be lw, or it might be addiu to $sp or
- $pc. We assume it's load. */
- info->insn_type = dis_dref;
- info->data_size = 4;
- break;
- case 'C':
- nbits = 8;
- shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- info->insn_type = dis_dref;
- info->data_size = 8;
- break;
- case 'U':
- nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- extu = 1;
- break;
- case 'k':
- nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- signedp = 1;
- break;
- case 'K':
- nbits = 8;
- shift = 3;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- signedp = 1;
- break;
- case 'p':
- nbits = 8;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- signedp = 1;
- pcrel = 1;
- branch = 1;
- break;
- case 'q':
- nbits = 11;
- immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
- signedp = 1;
- pcrel = 1;
- branch = 1;
- break;
- case 'A':
- nbits = 8;
- shift = 2;
- immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
- pcrel = 1;
- /* FIXME: This can be lw or la. We assume it is lw. */
- info->insn_type = dis_dref;
- info->data_size = 4;
- break;
- case 'B':
- nbits = 5;
- shift = 3;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
- pcrel = 1;
- info->insn_type = dis_dref;
- info->data_size = 8;
- break;
- case 'E':
- nbits = 5;
- shift = 2;
- immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
- pcrel = 1;
- break;
- default:
- abort ();
- }
+ /* Statics $ax - $a3. */
+ if (nstatics == 1)
+ infprintf (is, ",%s", mips_gpr_names[7]);
+ else if (nstatics > 0)
+ infprintf (is, ",%s-%s",
+ mips_gpr_names[7 - nstatics + 1],
+ mips_gpr_names[7]);
+ break;
+ }
- if (! use_extend)
- {
- if (signedp && immed >= (1 << (nbits - 1)))
- immed -= 1 << nbits;
- immed <<= shift;
- if ((type == '<' || type == '>' || type == '[' || type == ']')
- && immed == 0)
- immed = 8;
- }
- else
- {
- if (extbits == 16)
- immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
- else if (extbits == 15)
- immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
- else
- immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
- immed &= (1 << extbits) - 1;
- if (! extu && immed >= (1 << (extbits - 1)))
- immed -= 1 << extbits;
- }
+ if (is_offset && operand->type == OP_INT)
+ {
+ const struct mips_int_operand *int_op;
- if (! pcrel)
- (*info->fprintf_func) (info->stream, "%d", immed);
- else
- {
- bfd_vma baseaddr;
+ int_op = (const struct mips_int_operand *) operand;
+ info->insn_type = dis_dref;
+ info->data_size = 1 << int_op->shift;
+ }
- if (branch)
- {
- immed *= 2;
- baseaddr = memaddr + 2;
- }
- else if (use_extend)
- baseaddr = memaddr - 2;
- else
- {
- int status;
- bfd_byte buffer[2];
-
- baseaddr = memaddr;
-
- /* If this instruction is in the delay slot of a jr
- instruction, the base address is the address of the
- jr instruction. If it is in the delay slot of jalr
- instruction, the base address is the address of the
- jalr instruction. This test is unreliable: we have
- no way of knowing whether the previous word is
- instruction or data. */
- status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
- info);
- if (status == 0
- && (((info->endian == BFD_ENDIAN_BIG
- ? bfd_getb16 (buffer)
- : bfd_getl16 (buffer))
- & 0xf800) == 0x1800))
- baseaddr = memaddr - 4;
- else
- {
- status = (*info->read_memory_func) (memaddr - 2, buffer,
- 2, info);
- if (status == 0
+ if (operand->size == 26)
+ /* In this case INSN is the first two bytes of the instruction
+ and EXTEND is the second two bytes. */
+ uval = ((insn & 0x1f) << 21) | ((insn & 0x3e0) << 11) | extend;
+ else
+ {
+ /* Calculate the full field value. */
+ uval = mips_extract_operand (operand, insn);
+ if (use_extend)
+ {
+ ext_operand = decode_mips16_operand (type, TRUE);
+ if (ext_operand != operand)
+ {
+ operand = ext_operand;
+ if (operand->size == 16)
+ uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
+ else if (operand->size == 15)
+ uval |= ((extend & 0xf) << 11) | (extend & 0x7f0);
+ else
+ uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
+ }
+ }
+ }
+
+ baseaddr = memaddr + 2;
+ if (operand->type == OP_PCREL)
+ {
+ const struct mips_pcrel_operand *pcrel_op;
+
+ pcrel_op = (const struct mips_pcrel_operand *) operand;
+ if (!pcrel_op->include_isa_bit && use_extend)
+ baseaddr = memaddr - 2;
+ else if (!pcrel_op->include_isa_bit)
+ {
+ bfd_byte buffer[2];
+
+ /* If this instruction is in the delay slot of a JR
+ instruction, the base address is the address of the
+ JR instruction. If it is in the delay slot of a JALR
+ instruction, the base address is the address of the
+ JALR instruction. This test is unreliable: we have
+ no way of knowing whether the previous word is
+ instruction or data. */
+ if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
+ && (((info->endian == BFD_ENDIAN_BIG
+ ? bfd_getb16 (buffer)
+ : bfd_getl16 (buffer))
+ & 0xf800) == 0x1800))
+ baseaddr = memaddr - 4;
+ else if (info->read_memory_func (memaddr - 2, buffer, 2,
+ info) == 0
&& (((info->endian == BFD_ENDIAN_BIG
? bfd_getb16 (buffer)
: bfd_getl16 (buffer))
& 0xf81f) == 0xe800))
- baseaddr = memaddr - 2;
- }
- }
- info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
- if (pcrel && branch
- && info->flavour == bfd_target_unknown_flavour)
- /* For gdb disassembler, maintain odd address. */
- info->target |= 1;
- (*info->print_address_func) (info->target, info);
- }
- }
- break;
-
- case 'a':
- {
- int jalx = l & 0x400;
-
- if (! use_extend)
- extend = 0;
- l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
- if (!jalx && info->flavour == bfd_target_unknown_flavour)
- /* For gdb disassembler, maintain odd address. */
- l |= 1;
- }
- info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
- (*info->print_address_func) (info->target, info);
- break;
-
- case 'l':
- case 'L':
- {
- int need_comma, amask, smask;
-
- need_comma = 0;
-
- l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
-
- amask = (l >> 3) & 7;
-
- if (amask > 0 && amask < 5)
- {
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
- if (amask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[amask + 3]);
- need_comma = 1;
- }
-
- smask = (l >> 1) & 3;
- if (smask == 3)
- {
- (*info->fprintf_func) (info->stream, "%s??",
- need_comma ? "," : "");
- need_comma = 1;
- }
- else if (smask > 0)
- {
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[16]);
- if (smask > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[smask + 15]);
- need_comma = 1;
- }
-
- if (l & 1)
- {
- (*info->fprintf_func) (info->stream, "%s%s",
- need_comma ? "," : "",
- mips_gpr_names[31]);
- need_comma = 1;
- }
+ baseaddr = memaddr - 2;
+ else
+ baseaddr = memaddr;
+ }
+ }
- if (amask == 5 || amask == 6)
- {
- (*info->fprintf_func) (info->stream, "%s$f0",
- need_comma ? "," : "");
- if (amask == 6)
- (*info->fprintf_func) (info->stream, "-$f1");
- }
- }
+ print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval);
break;
+ }
+}
- case 'm':
- case 'M':
- /* MIPS16e save/restore. */
- {
- int need_comma = 0;
- int amask, args, statics;
- int nsreg, smask;
- int framesz;
- int i, j;
-
- l = l & 0x7f;
- if (use_extend)
- l |= extend << 16;
-
- amask = (l >> 16) & 0xf;
- if (amask == MIPS16_ALL_ARGS)
- {
- args = 4;
- statics = 0;
- }
- else if (amask == MIPS16_ALL_STATICS)
- {
- args = 0;
- statics = 4;
- }
- else
- {
- args = amask >> 2;
- statics = amask & 3;
- }
-
- if (args > 0) {
- (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
- if (args > 1)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[4 + args - 1]);
- need_comma = 1;
- }
- framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
- if (framesz == 0 && !use_extend)
- framesz = 128;
-
- (*info->fprintf_func) (info->stream, "%s%d",
- need_comma ? "," : "",
- framesz);
-
- if (l & 0x40) /* $ra */
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
-
- nsreg = (l >> 24) & 0x7;
- smask = 0;
- if (l & 0x20) /* $s0 */
- smask |= 1 << 0;
- if (l & 0x10) /* $s1 */
- smask |= 1 << 1;
- if (nsreg > 0) /* $s2-$s8 */
- smask |= ((1 << nsreg) - 1) << 2;
-
- /* Find first set static reg bit. */
- for (i = 0; i < 9; i++)
- {
- if (smask & (1 << i))
- {
- (*info->fprintf_func) (info->stream, ",%s",
- mips_gpr_names[i == 8 ? 30 : (16 + i)]);
- /* Skip over string of set bits. */
- for (j = i; smask & (2 << j); j++)
- continue;
- if (j > i)
- (*info->fprintf_func) (info->stream, "-%s",
- mips_gpr_names[j == 8 ? 30 : (16 + j)]);
- i = j + 1;
- }
- }
-
- /* Statics $ax - $a3. */
- if (statics == 1)
- (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
- else if (statics > 0)
- (*info->fprintf_func) (info->stream, ",%s-%s",
- mips_gpr_names[7 - statics + 1],
- mips_gpr_names[7]);
- }
- break;
+/* Check if the given address is the last word of a MIPS16 PLT entry.
+ This word is data and depending on the value it may interfere with
+ disassembly of further PLT entries. We make use of the fact PLT
+ symbols are marked BSF_SYNTHETIC. */
+static bfd_boolean
+is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr)
+{
+ if (info->symbols
+ && info->symbols[0]
+ && (info->symbols[0]->flags & BSF_SYNTHETIC)
+ && addr == bfd_asymbol_value (info->symbols[0]) + 12)
+ return TRUE;
- default:
- /* xgettext:c-format */
- (*info->fprintf_func)
- (info->stream,
- _("# internal disassembler error, unrecognised modifier (%c)"),
- type);
- abort ();
- }
+ return FALSE;
}
/* Disassemble mips16 instructions. */
@@ -2112,24 +1688,50 @@ print_mips16_insn_arg (char type,
static int
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
{
+ const fprintf_ftype infprintf = info->fprintf_func;
int status;
- bfd_byte buffer[2];
+ bfd_byte buffer[4];
int length;
int insn;
bfd_boolean use_extend;
int extend = 0;
const struct mips_opcode *op, *opend;
+ struct mips_print_arg_state state;
+ void *is = info->stream;
info->bytes_per_chunk = 2;
info->display_endian = info->endian;
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
info->data_size = 0;
- info->insn_type = dis_nonbranch;
info->target = 0;
info->target2 = 0;
- status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+#define GET_OP(insn, field) \
+ (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
+ /* Decode PLT entry's GOT slot address word. */
+ if (is_mips16_plt_tail (info, memaddr))
+ {
+ info->insn_type = dis_noninsn;
+ status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+ if (status == 0)
+ {
+ unsigned int gotslot;
+
+ if (info->endian == BFD_ENDIAN_BIG)
+ gotslot = bfd_getb32 (buffer);
+ else
+ gotslot = bfd_getl32 (buffer);
+ infprintf (is, ".word\t0x%x", gotslot);
+
+ return 4;
+ }
+ }
+ else
+ {
+ info->insn_type = dis_nonbranch;
+ status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+ }
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
@@ -2155,8 +1757,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
@@ -2169,8 +1770,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
/* Check for an extend opcode followed by an extend opcode. */
if ((insn & 0xf800) == 0xf000)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length;
}
@@ -2189,12 +1789,11 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
{
const char *s;
- if (strchr (op->args, 'a') != NULL)
+ if (op->args[0] == 'a' || op->args[0] == 'i')
{
if (use_extend)
{
- (*info->fprintf_func) (info->stream, "extend 0x%x",
- (unsigned int) extend);
+ infprintf (is, "extend 0x%x", (unsigned int) extend);
info->insn_type = dis_noninsn;
return length - 2;
}
@@ -2216,16 +1815,16 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
}
}
- (*info->fprintf_func) (info->stream, "%s", op->name);
+ infprintf (is, "%s", op->name);
if (op->args[0] != '\0')
- (*info->fprintf_func) (info->stream, "\t");
+ infprintf (is, "\t");
+ init_print_arg_state (&state);
for (s = op->args; *s != '\0'; s++)
{
if (*s == ','
&& s[1] == 'w'
- && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
- == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
+ && GET_OP (insn, RX) == GET_OP (insn, RY))
{
/* Skip the register and the comma. */
++s;
@@ -2233,38 +1832,38 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
}
if (*s == ','
&& s[1] == 'v'
- && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
- == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
+ && GET_OP (insn, RZ) == GET_OP (insn, RX))
{
/* Skip the register and the comma. */
++s;
continue;
}
- print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
- info);
+ print_mips16_insn_arg (info, &state, op, *s, memaddr, insn,
+ use_extend, extend, s[1] == '(');
}
/* Figure out branch instruction type and delay slot information. */
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
info->branch_delay_insns = 1;
- if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
- | MIPS16_INSN_UNCOND_BRANCH)) != 0)
+ if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
+ || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0)
{
if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
info->insn_type = dis_jsr;
else
info->insn_type = dis_branch;
}
- else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
+ else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
info->insn_type = dis_condbranch;
return length;
}
}
+#undef GET_OP
if (use_extend)
- (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
- (*info->fprintf_func) (info->stream, "0x%x", insn);
+ infprintf (is, "0x%x", extend | 0xf000);
+ infprintf (is, "0x%x", insn);
info->insn_type = dis_noninsn;
return length;
@@ -2277,19 +1876,12 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
{
const fprintf_ftype infprintf = info->fprintf_func;
const struct mips_opcode *op, *opend;
- unsigned int lsb, msbd, msb;
void *is = info->stream;
- unsigned int regno;
bfd_byte buffer[2];
- int lastregno = 0;
- int higher;
- int length;
+ unsigned int higher;
+ unsigned int length;
int status;
- int delta;
- int immed;
- int insn;
-
- lsb = 0;
+ unsigned int insn;
info->bytes_per_chunk = 2;
info->display_endian = info->endian;
@@ -2373,8 +1965,6 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
/* FIXME: Should probably use a hash table on the major opcode here. */
-#define GET_OP(insn, field) \
- (((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
opend = micromips_opcodes + bfd_micromips_num_opcodes;
for (op = micromips_opcodes; op < opend; op++)
{
@@ -2384,543 +1974,13 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
&& ((length == 2 && (op->mask & 0xffff0000) == 0)
|| (length == 4 && (op->mask & 0xffff0000) != 0)))
{
- const char *s;
-
infprintf (is, "%s", op->name);
- if (op->args[0] != '\0')
- infprintf (is, "\t");
- for (s = op->args; *s != '\0'; s++)
+ if (op->args[0])
{
- switch (*s)
- {
- case ',':
- case '(':
- case ')':
- infprintf (is, "%c", *s);
- break;
-
- case '.':
- delta = GET_OP (insn, OFFSET10);
- if (delta & 0x200)
- delta |= ~0x3ff;
- infprintf (is, "%d", delta);
- break;
-
- case '1':
- infprintf (is, "0x%lx", GET_OP (insn, STYPE));
- break;
-
- case '<':
- infprintf (is, "0x%lx", GET_OP (insn, SHAMT));
- break;
-
- case '\\':
- infprintf (is, "0x%lx", GET_OP (insn, 3BITPOS));
- break;
-
- case '|':
- infprintf (is, "0x%lx", GET_OP (insn, TRAP));
- break;
-
- case '~':
- delta = GET_OP (insn, OFFSET12);
- if (delta & 0x800)
- delta |= ~0x7ff;
- infprintf (is, "%d", delta);
- break;
-
- case 'a':
- if (strcmp (op->name, "jalx") == 0)
- info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff)
- | (GET_OP (insn, TARGET) << 2));
- else
- info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
- | ((GET_OP (insn, TARGET)) << 1));
- /* For gdb disassembler, force odd address on jalx. */
- if (info->flavour == bfd_target_unknown_flavour
- && strcmp (op->name, "jalx") == 0)
- info->target |= 1;
- (*info->print_address_func) (info->target, info);
- break;
-
- case 'b':
- case 'r':
- case 's':
- case 'v':
- infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]);
- break;
-
- case 'c':
- infprintf (is, "0x%lx", GET_OP (insn, CODE));
- break;
-
- case 'd':
- infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]);
- break;
-
- case 'h':
- infprintf (is, "0x%lx", GET_OP (insn, PREFX));
- break;
-
- case 'i':
- case 'u':
- infprintf (is, "0x%lx", GET_OP (insn, IMMEDIATE));
- break;
-
- case 'j': /* Same as i, but sign-extended. */
- case 'o':
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
- infprintf (is, "%d", delta);
- break;
-
- case 'k':
- infprintf (is, "0x%x", GET_OP (insn, CACHE));
- break;
-
- case 'n':
- {
- int s_reg_encode;
-
- immed = GET_OP (insn, RT);
- s_reg_encode = immed & 0xf;
- if (s_reg_encode != 0)
- {
- if (s_reg_encode == 1)
- infprintf (is, "%s", mips_gpr_names[16]);
- else if (s_reg_encode < 9)
- infprintf (is, "%s-%s",
- mips_gpr_names[16],
- mips_gpr_names[15 + s_reg_encode]);
- else if (s_reg_encode == 9)
- infprintf (is, "%s-%s,%s",
- mips_gpr_names[16],
- mips_gpr_names[23],
- mips_gpr_names[30]);
- else
- infprintf (is, "UNKNOWN");
- }
-
- if (immed & 0x10) /* For ra. */
- {
- if (s_reg_encode == 0)
- infprintf (is, "%s", mips_gpr_names[31]);
- else
- infprintf (is, ",%s", mips_gpr_names[31]);
- }
- break;
- }
-
- case 'p':
- /* Sign-extend the displacement. */
- delta = (GET_OP (insn, DELTA) ^ 0x8000) - 0x8000;
- info->target = (delta << 1) + memaddr + length;
- (*info->print_address_func) (info->target, info);
- break;
-
- case 'q':
- infprintf (is, "0x%lx", GET_OP (insn, CODE2));
- break;
-
- case 't':
- case 'w':
- infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]);
- break;
-
- case 'y':
- infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]);
- break;
-
- case 'z':
- infprintf (is, "%s", mips_gpr_names[0]);
- break;
-
- case 'B':
- infprintf (is, "0x%lx", GET_OP (insn, CODE10));
- break;
-
- case 'C':
- infprintf (is, "0x%lx", GET_OP (insn, COPZ));
- break;
-
- case 'D':
- infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]);
- break;
-
- case 'E':
- /* Coprocessor register for lwcN instructions, et al.
-
- Note that there is no load/store cp0 instructions, and
- that FPU (cp1) instructions disassemble this field using
- 'T' format. Therefore, until we gain understanding of
- cp2 register names, we can simply print the register
- numbers. */
- infprintf (is, "$%ld", GET_OP (insn, RT));
- break;
-
- case 'G':
- /* Coprocessor register for mtcN instructions, et al. Note
- that FPU (cp1) instructions disassemble this field using
- 'S' format. Therefore, we only need to worry about cp0,
- cp2, and cp3.
- The microMIPS encoding does not have a coprocessor
- identifier field as such, so we must work out the
- coprocessor number by looking at the opcode. */
- switch (insn
- & ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
- | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)))
- {
- case 0x000000fc: /* mfc0 */
- case 0x000002fc: /* mtc0 */
- case 0x580000fc: /* dmfc0 */
- case 0x580002fc: /* dmtc0 */
- infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
- break;
- default:
- infprintf (is, "$%ld", GET_OP (insn, RS));
- break;
- }
- break;
-
- case 'H':
- infprintf (is, "%ld", GET_OP (insn, SEL));
- break;
-
- case 'K':
- infprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]);
- break;
-
- case 'M':
- infprintf (is, "$fcc%ld", GET_OP (insn, CCC));
- break;
-
- case 'N':
- infprintf (is,
- (op->pinfo & (FP_D | FP_S)) != 0
- ? "$fcc%ld" : "$cc%ld",
- GET_OP (insn, BCC));
- break;
-
- case 'R':
- infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]);
- break;
-
- case 'S':
- case 'V':
- infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]);
- break;
-
- case 'T':
- infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]);
- break;
-
- case '+':
- /* Extension character; switch for second char. */
- s++;
- switch (*s)
- {
- case 'A':
- lsb = GET_OP (insn, EXTLSB);
- infprintf (is, "0x%x", lsb);
- break;
-
- case 'B':
- msb = GET_OP (insn, INSMSB);
- infprintf (is, "0x%x", msb - lsb + 1);
- break;
-
- case 'C':
- case 'H':
- msbd = GET_OP (insn, EXTMSBD);
- infprintf (is, "0x%x", msbd + 1);
- break;
-
- case 'D':
- {
- const struct mips_cp0sel_name *n;
- unsigned int cp0reg, sel;
-
- cp0reg = GET_OP (insn, RS);
- sel = GET_OP (insn, SEL);
-
- /* CP0 register including 'sel' code for mtcN
- (et al.), to be printed textually if known.
- If not known, print both CP0 register name and
- sel numerically since CP0 register with sel 0 may
- have a name unrelated to register being printed. */
- n = lookup_mips_cp0sel_name (mips_cp0sel_names,
- mips_cp0sel_names_len,
- cp0reg, sel);
- if (n != NULL)
- infprintf (is, "%s", n->name);
- else
- infprintf (is, "$%d,%d", cp0reg, sel);
- break;
- }
-
- case 'E':
- lsb = GET_OP (insn, EXTLSB) + 32;
- infprintf (is, "0x%x", lsb);
- break;
-
- case 'F':
- msb = GET_OP (insn, INSMSB) + 32;
- infprintf (is, "0x%x", msb - lsb + 1);
- break;
-
- case 'G':
- msbd = GET_OP (insn, EXTMSBD) + 32;
- infprintf (is, "0x%x", msbd + 1);
- break;
-
- default:
- /* xgettext:c-format */
- infprintf (is,
- _("# internal disassembler error, "
- "unrecognized modifier (+%c)"),
- *s);
- abort ();
- }
- break;
-
- case 'm':
- /* Extension character; switch for second char. */
- s++;
- switch (*s)
- {
- case 'a': /* global pointer. */
- infprintf (is, "%s", mips_gpr_names[28]);
- break;
-
- case 'b':
- regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'c':
- regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'd':
- regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'e':
- regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'f':
- /* Save lastregno for "mt" to print out later. */
- lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)];
- infprintf (is, "%s", mips_gpr_names[lastregno]);
- break;
-
- case 'g':
- regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'h':
- regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'i':
- regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'j':
- infprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]);
- break;
-
- case 'l':
- regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'm':
- regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'n':
- regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'p':
- /* Save lastregno for "mt" to print out later. */
- lastregno = GET_OP (insn, MP);
- infprintf (is, "%s", mips_gpr_names[lastregno]);
- break;
-
- case 'q':
- regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)];
- infprintf (is, "%s", mips_gpr_names[regno]);
- break;
-
- case 'r': /* program counter. */
- infprintf (is, "$pc");
- break;
-
- case 's': /* stack pointer. */
- lastregno = 29;
- infprintf (is, "%s", mips_gpr_names[29]);
- break;
-
- case 't':
- infprintf (is, "%s", mips_gpr_names[lastregno]);
- break;
-
- case 'z': /* $0. */
- infprintf (is, "%s", mips_gpr_names[0]);
- break;
-
- case 'A':
- /* Sign-extend the immediate. */
- immed = ((GET_OP (insn, IMMA) ^ 0x40) - 0x40) << 2;
- infprintf (is, "%d", immed);
- break;
-
- case 'B':
- immed = micromips_imm_b_map[GET_OP (insn, IMMB)];
- infprintf (is, "%d", immed);
- break;
-
- case 'C':
- immed = micromips_imm_c_map[GET_OP (insn, IMMC)];
- infprintf (is, "0x%lx", immed);
- break;
-
- case 'D':
- /* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMMD) ^ 0x200) - 0x200;
- info->target = (delta << 1) + memaddr + length;
- (*info->print_address_func) (info->target, info);
- break;
-
- case 'E':
- /* Sign-extend the displacement. */
- delta = (GET_OP (insn, IMME) ^ 0x40) - 0x40;
- info->target = (delta << 1) + memaddr + length;
- (*info->print_address_func) (info->target, info);
- break;
-
- case 'F':
- immed = GET_OP (insn, IMMF);
- infprintf (is, "0x%x", immed);
- break;
-
- case 'G':
- immed = (insn >> MICROMIPSOP_SH_IMMG) + 1;
- immed = (immed & MICROMIPSOP_MASK_IMMG) - 1;
- infprintf (is, "%d", immed);
- break;
-
- case 'H':
- immed = GET_OP (insn, IMMH) << 1;
- infprintf (is, "%d", immed);
- break;
-
- case 'I':
- immed = (insn >> MICROMIPSOP_SH_IMMI) + 1;
- immed = (immed & MICROMIPSOP_MASK_IMMI) - 1;
- infprintf (is, "%d", immed);
- break;
-
- case 'J':
- immed = GET_OP (insn, IMMJ) << 2;
- infprintf (is, "%d", immed);
- break;
-
- case 'L':
- immed = GET_OP (insn, IMML);
- infprintf (is, "%d", immed);
- break;
-
- case 'M':
- immed = (insn >> MICROMIPSOP_SH_IMMM) - 1;
- immed = (immed & MICROMIPSOP_MASK_IMMM) + 1;
- infprintf (is, "%d", immed);
- break;
-
- case 'N':
- immed = GET_OP (insn, IMMN);
- if (immed == 0)
- infprintf (is, "%s,%s",
- mips_gpr_names[16],
- mips_gpr_names[31]);
- else
- infprintf (is, "%s-%s,%s",
- mips_gpr_names[16],
- mips_gpr_names[16 + immed],
- mips_gpr_names[31]);
- break;
-
- case 'O':
- immed = GET_OP (insn, IMMO);
- infprintf (is, "0x%x", immed);
- break;
-
- case 'P':
- immed = GET_OP (insn, IMMP) << 2;
- infprintf (is, "%d", immed);
- break;
-
- case 'Q':
- /* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMQ) ^ 0x400000) - 0x400000;
- immed <<= 2;
- infprintf (is, "%d", immed);
- break;
-
- case 'U':
- immed = GET_OP (insn, IMMU) << 2;
- infprintf (is, "%d", immed);
- break;
-
- case 'W':
- immed = GET_OP (insn, IMMW) << 2;
- infprintf (is, "%d", immed);
- break;
-
- case 'X':
- /* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMX) ^ 0x8) - 0x8;
- infprintf (is, "%d", immed);
- break;
-
- case 'Y':
- /* Sign-extend the immediate. */
- immed = (GET_OP (insn, IMMY) ^ 0x100) - 0x100;
- if (immed >= -2 && immed <= 1)
- immed ^= 0x100;
- immed = immed << 2;
- infprintf (is, "%d", immed);
- break;
-
- default:
- /* xgettext:c-format */
- infprintf (is,
- _("# internal disassembler error, "
- "unrecognized modifier (m%c)"),
- *s);
- abort ();
- }
- break;
-
- default:
- /* xgettext:c-format */
- infprintf (is,
- _("# internal disassembler error, "
- "unrecognized modifier (%c)"),
- *s);
- abort ();
- }
+ infprintf (is, "\t");
+ print_insn_args (info, op, decode_micromips_operand, insn,
+ memaddr + length + 1);
}
/* Figure out instruction type and branch delay information. */
@@ -2930,7 +1990,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
| (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
{
- if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
+ if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0)
info->insn_type = dis_jsr;
else
info->insn_type = dis_branch;
@@ -2944,13 +2004,12 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
info->insn_type = dis_condbranch;
}
else if ((op->pinfo
- & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
+ & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0)
info->insn_type = dis_dref;
return length;
}
}
-#undef GET_OP
infprintf (is, "0x%x", insn);
info->insn_type = dis_noninsn;
@@ -2969,24 +2028,26 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
static bfd_boolean
is_compressed_mode_p (struct disassemble_info *info)
{
- elf_symbol_type *symbol;
- int pos;
int i;
-
- for (i = 0; i < info->num_symbols; i++)
- {
- pos = info->symtab_pos + i;
-
- if (bfd_asymbol_flavour (info->symtab[pos]) != bfd_target_elf_flavour)
- continue;
-
- symbol = (elf_symbol_type *) info->symtab[pos];
- if ((!micromips_ase
- && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
- || (micromips_ase
- && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
- return 1;
- }
+ int l;
+
+ for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++)
+ if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0
+ && ((!micromips_ase
+ && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i))
+ || (micromips_ase
+ && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i))))
+ return 1;
+ else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour
+ && info->symtab[i]->section == info->section)
+ {
+ elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i];
+ if ((!micromips_ase
+ && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
+ || (micromips_ase
+ && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
+ return 1;
+ }
return 0;
}
@@ -3031,12 +2092,12 @@ _print_insn_mips (bfd_vma memaddr,
status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
if (status == 0)
{
- unsigned long insn;
+ int insn;
if (endianness == BFD_ENDIAN_BIG)
- insn = (unsigned long) bfd_getb32 (buffer);
+ insn = bfd_getb32 (buffer);
else
- insn = (unsigned long) bfd_getl32 (buffer);
+ insn = bfd_getl32 (buffer);
return print_insn_mips (memaddr, insn, info);
}
@@ -3069,6 +2130,12 @@ The following MIPS specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
+ msa Recognize MSA instructions.\n"));
+
+ fprintf (stream, _("\n\
+ virt Recognize the virtualization ASE instructions.\n"));
+
+ fprintf (stream, _("\n\
gpr-names=ABI Print GPR names according to specified ABI.\n\
Default: based on binary being disassembled.\n"));
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