GDB 7.6.50

sim/erc32/float.c

 /*
  * This file is part of SIS.
  *
  * SIS, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, European
  * Space Agency
  *
  * This program is free software; you can redistribute it and/or modify it under
  * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
+ * Software Foundation; either version 3 of the License, or (at your option)
  * any later version.
  *
  * This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675
- * Mass Ave, Cambridge, MA 02139, USA.
+ * this program; if not, see <http://www.gnu.org/licenses/>.
  *
  *
  * This file implements the interface between the host and the simulated
  * FPU. IEEE trap handling is done as follows: 
  * 1. In the host, all IEEE traps are masked
  * 2. After each simulated FPU instruction, check if any exception occured 
  *    by reading the exception bits from the host FPU status register 
  *    (get_accex()).
  * 3. Propagate any exceptions to the simulated FSR.
  * 4. Clear host exception bits
  *
  *
  * This can also be done using ieee_flags() library routine on sun.
  */
 
+#include "config.h"
 #include "sis.h"
 
 /* Forward declarations */
 
 extern uint32   _get_sw PARAMS ((void));
 extern uint32   _get_cw PARAMS ((void));
 static void     __setfpucw PARAMS ((unsigned short fpu_control));
 
 /* This host dependent routine should return the accrued exceptions */
 int
@@ skipping 39 matching lines @@
 {
 #ifdef sparc
         _set_fsr_raw(fsr & ~0x0f800000);
 #elif i386
      void __setfpucw(unsigned short fpu_control);
      uint32 rawfsr;
 
      fsr >>= 30;
      switch (fsr) {
         case 0: 
-        case 2: break;
-        case 1: fsr = 3;
-        case 3: fsr = 1;
+        case 2:
+          break;
+
+        case 1:
+          fsr = 3;
+          break;
+
+        case 3:
+          fsr = 1;
+          break;
      }
      rawfsr = _get_cw();
      rawfsr |= (fsr << 10) | 0x3ff;
      __setfpucw(rawfsr);
 #else
 #warning no fpu trap support for this target
 #endif
 }
 
 
@@ skipping 96 matching lines @@
   
   /* mask in */
   cw &= _FPU_RESERVED;
   cw = cw | (fpu_control & ~_FPU_RESERVED);
 
   /* set cw */
   __asm__ volatile ("fldcw %0" :: "m" (cw));
 }
 /* #endif */
 #endif