sim/cr16/cr16_sim.h - Issue 124383005: GDB 7.6.50

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Side by Side Diff: sim/cr16/cr16_sim.h

Issue 124383005: GDB 7.6.50 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@upstream

Patch Set: Created 6 years, 11 months ago

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1 /* Simulation code for the CR16 processor.	1 /* Simulation code for the CR16 processor.

2 Copyright (C) 2008-2012 Free Software Foundation, Inc.	2 Copyright (C) 2008-2013 Free Software Foundation, Inc.

3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>	3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>

4	4

5 This file is part of GDB, the GNU debugger.	5 This file is part of GDB, the GNU debugger.

6	6

7 This program is free software; you can redistribute it and/or modify	7 This program is free software; you can redistribute it and/or modify

8 it under the terms of the GNU General Public License as published by	8 it under the terms of the GNU General Public License as published by

9 the Free Software Foundation; either version 3, or (at your option)	9 the Free Software Foundation; either version 3, or (at your option)

10 any later version.	10 any later version.

11	11

12 This program is distributed in the hope that it will be useful,	12 This program is distributed in the hope that it will be useful,

(...skipping 452 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
465 #define ATRC_VECTOR_START 0xFFFC0C /alternate trace trap /	465 #define ATRC_VECTOR_START 0xFFFC0C /alternate trace trap /

466 #define ABPT_VECTOR_START 0xFFFC0E /alternate break point trap /	466 #define ABPT_VECTOR_START 0xFFFC0E /alternate break point trap /

467	467

468	468

469 /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in	469 /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in

470 cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) \|	470 cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) \|

471 (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for	471 (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for

472 PSR is masked for zero bits. */	472 PSR is masked for zero bits. */

473	473

474 extern creg_t move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p);	474 extern creg_t move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p);

	475

	476 #ifndef SIGTRAP

	477 #define SIGTRAP 5

	478 #endif

	479 /* Special purpose trap */

	480 #define TRAP_BREAKPOINT 8

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