GDB 7.6.50

opcodes/i386-opc.h

 /* Declarations for Intel 80386 opcode table
    Copyright 2007, 2008, 2009, 2010, 2012
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
    This library is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3, or (at your option)
    any later version.
@@ skipping 76 matching lines @@
   /* ABM New Instructions required */
   CpuABM,
   /* SSE4.1 support required */
   CpuSSE4_1,
   /* SSE4.2 support required */
   CpuSSE4_2,
   /* AVX support required */
   CpuAVX,
   /* AVX2 support required */
   CpuAVX2,
+  /* Intel AVX-512 Foundation Instructions support required */
+  CpuAVX512F,
+  /* Intel AVX-512 Conflict Detection Instructions support required */
+  CpuAVX512CD,
+  /* Intel AVX-512 Exponential and Reciprocal Instructions support
+     required */
+  CpuAVX512ER,
+  /* Intel AVX-512 Prefetch Instructions support required */
+  CpuAVX512PF,
   /* Intel L1OM support required */
   CpuL1OM,
   /* Intel K1OM support required */
   CpuK1OM,
   /* Xsave/xrstor New Instructions support required */
   CpuXsave,
   /* Xsaveopt New Instructions support required */
   CpuXsaveopt,
   /* AES support required */
   CpuAES,
   /* PCLMUL support required */
   CpuPCLMUL,
   /* FMA support required */
   CpuFMA,
   /* FMA4 support required */
   CpuFMA4,
   /* XOP support required */
   CpuXOP,
   /* LWP support required */
   CpuLWP,
   /* BMI support required */
   CpuBMI,
   /* TBM support required */
   CpuTBM,
   /* MOVBE Instruction support required */
   CpuMovbe,
+  /* CMPXCHG16B instruction support required.  */
+  CpuCX16,
   /* EPT Instructions required */
   CpuEPT,
   /* RDTSCP Instruction support required */
   CpuRdtscp,
   /* FSGSBASE Instructions required */
   CpuFSGSBase,
   /* RDRND Instructions required */
   CpuRdRnd,
   /* F16C Instructions required */
   CpuF16C,
   /* Intel BMI2 support required */
   CpuBMI2,
   /* LZCNT support required */
   CpuLZCNT,
   /* HLE support required */
   CpuHLE,
   /* RTM support required */
   CpuRTM,
   /* INVPCID Instructions required */
   CpuINVPCID,
   /* VMFUNC Instruction required */
   CpuVMFUNC,
+  /* Intel MPX Instructions required  */
+  CpuMPX,
   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,
   /* RDRSEED instruction required.  */
   CpuRDSEED,
   /* Multi-presisionn add-carry instructions are required.  */
   CpuADX,
-  /* Supports prefetchw instruction.  */
+  /* Supports prefetchw and prefetch instructions.  */
   CpuPRFCHW,
+  /* SMAP instructions required.  */
+  CpuSMAP,
+  /* SHA instructions required.  */
+  CpuSHA,
+  /* VREX support required  */
+  CpuVREX,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
   CpuNo64,
   /* The last bitfield in i386_cpu_flags.  */
   CpuMax = CpuNo64
 };
 
 #define CpuNumOfUints \
   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
@@ skipping 34 matching lines @@
       unsigned int cpusvme:1;
       unsigned int cpuvmx:1;
       unsigned int cpusmx:1;
       unsigned int cpussse3:1;
       unsigned int cpusse4a:1;
       unsigned int cpuabm:1;
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpuavx:1;
       unsigned int cpuavx2:1;
+      unsigned int cpuavx512f:1;
+      unsigned int cpuavx512cd:1;
+      unsigned int cpuavx512er:1;
+      unsigned int cpuavx512pf:1;
       unsigned int cpul1om:1;
       unsigned int cpuk1om:1;
       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
       unsigned int cpupclmul:1;
       unsigned int cpufma:1;
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
       unsigned int cpubmi:1;
       unsigned int cputbm:1;
       unsigned int cpumovbe:1;
+      unsigned int cpucx16:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
       unsigned int cpufsgsbase:1;
       unsigned int cpurdrnd:1;
       unsigned int cpuf16c:1;
       unsigned int cpubmi2:1;
       unsigned int cpulzcnt:1;
       unsigned int cpuhle:1;
       unsigned int cpurtm:1;
       unsigned int cpuinvpcid:1;
       unsigned int cpuvmfunc:1;
+      unsigned int cpumpx:1;
       unsigned int cpulm:1;
       unsigned int cpurdseed:1;
       unsigned int cpuadx:1;
       unsigned int cpuprfchw:1;
+      unsigned int cpusmap:1;
+      unsigned int cpusha:1;
+      unsigned int cpuvrex:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
 #endif
     } bitfield;
   unsigned int array[CpuNumOfUints];
 } i386_cpu_flags;
 
 /* Position of opcode_modifier bits.  */
@@ skipping 47 matching lines @@
   /* s suffix on instruction illegal */
   No_sSuf,
   /* q suffix on instruction illegal */
   No_qSuf,
   /* long double suffix on instruction illegal */
   No_ldSuf,
   /* instruction needs FWAIT */
   FWait,
   /* quick test for string instructions */
   IsString,
+  /* quick test if branch instruction is MPX supported */
+  BNDPrefixOk,
   /* quick test for lockable instructions */
   IsLockable,
   /* fake an extra reg operand for clr, imul and special register
      processing for some instructions.  */
   RegKludge,
   /* The first operand must be xmm0 */
   FirstXmm0,
   /* An implicit xmm0 as the first operand */
   Implicit1stXmm0,
   /* The HLE prefix is OK:
@@ skipping 82 matching lines @@
      2: 3 source operands.
    */
 #define XOP2SOURCES     1
 #define VEX3SOURCES     2
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
   /* Instruction with vector SIB byte:
         1: 128bit vector register.
         2: 256bit vector register.
+        3: 512bit vector register.
    */
 #define VecSIB128       1
 #define VecSIB256       2
+#define VecSIB512       3
   VecSIB,
   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */
   NoAVX,
+
+  /* insn has EVEX prefix:
+        1: 512bit EVEX prefix.
+        2: 128bit EVEX prefix.
+        3: 256bit EVEX prefix.
+        4: Length-ignored (LIG) EVEX prefix.
+   */
+#define EVEX512                1
+#define EVEX128                2
+#define EVEX256                3
+#define EVEXLIG                4
+  EVex,
+
+  /* AVX512 masking support:
+        1: Zeroing-masking.
+        2: Merging-masking.
+        3: Both zeroing and merging masking.
+   */
+#define ZEROING_MASKING 1
+#define MERGING_MASKING 2
+#define BOTH_MASKING    3
+  Masking,
+
+  /* Input element size of vector insn:
+        0: 32bit.
+        1: 64bit.
+   */
+  VecESize,
+
+  /* Broadcast factor.
+        0: No broadcast.
+        1: 1to16 broadcast.
+        2: 1to8 broadcast.
+   */
+#define NO_BROADCAST    0
+#define BROADCAST_1TO16 1
+#define BROADCAST_1TO8  2
+  Broadcast,
+
+  /* Static rounding control is supported.  */
+  StaticRounding,
+
+  /* Supress All Exceptions is supported.  */
+  SAE,
+
+  /* Copressed Disp8*N attribute.  */
+  Disp8MemShift,
+
+  /* Default mask isn't allowed.  */
+  NoDefMask,
+
   /* Compatible with old (<= 2.8.1) versions of gcc  */
   OldGcc,
   /* AT&T mnemonic.  */
   ATTMnemonic,
   /* AT&T syntax.  */
   ATTSyntax,
   /* Intel syntax.  */
   IntelSyntax,
   /* The last bitfield in i386_opcode_modifier.  */
   Opcode_Modifier_Max
@@ skipping 20 matching lines @@
   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
   unsigned int no_bsuf:1;
   unsigned int no_wsuf:1;
   unsigned int no_lsuf:1;
   unsigned int no_ssuf:1;
   unsigned int no_qsuf:1;
   unsigned int no_ldsuf:1;
   unsigned int fwait:1;
   unsigned int isstring:1;
+  unsigned int bndprefixok:1;
   unsigned int islockable:1;
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;
   unsigned int hleprefixok:2;
   unsigned int repprefixok:1;
   unsigned int todword:1;
   unsigned int toqword:1;
   unsigned int addrprefixop0:1;
   unsigned int isprefix:1;
   unsigned int immext:1;
   unsigned int norex64:1;
   unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
   unsigned int vexvvvv:2;
   unsigned int vexw:2;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
   unsigned int veximmext:1;
   unsigned int vecsib:2;
   unsigned int sse2avx:1;
   unsigned int noavx:1;
+  unsigned int evex:3;
+  unsigned int masking:2;
+  unsigned int vecesize:1;
+  unsigned int broadcast:3;
+  unsigned int staticrounding:1;
+  unsigned int sae:1;
+  unsigned int disp8memshift:3;
+  unsigned int nodefmask:1;
   unsigned int oldgcc:1;
   unsigned int attmnemonic:1;
   unsigned int attsyntax:1;
   unsigned int intelsyntax:1;
 } i386_opcode_modifier;
 
 /* Position of operand_type bits.  */
 
 enum
 {
   /* 8bit register */
   Reg8 = 0,
   /* 16bit register */
   Reg16,
   /* 32bit register */
   Reg32,
   /* 64bit register */
   Reg64,
   /* Floating pointer stack register */
   FloatReg,
   /* MMX register */
   RegMMX,
   /* SSE register */
   RegXMM,
   /* AVX registers */
   RegYMM,
+  /* AVX512 registers */
+  RegZMM,
+  /* Vector Mask registers */
+  RegMask,
   /* Control register */
   Control,
   /* Debug register */
   Debug,
   /* Test register */
   Test,
   /* 2 bit segment register */
   SReg2,
   /* 3 bit segment register */
   SReg3,
@@ skipping 59 matching lines @@
   /* FWORD memory. 6 byte */
   Fword,
   /* QWORD memory. 8 byte */
   Qword,
   /* TBYTE memory. 10 byte */
   Tbyte,
   /* XMMWORD memory. */
   Xmmword,
   /* YMMWORD memory. */
   Ymmword,
+  /* ZMMWORD memory.  */
+  Zmmword,
   /* Unspecified memory size.  */
   Unspecified,
   /* Any memory size.  */
   Anysize,
 
   /* Vector 4 bit immediate.  */
   Vec_Imm4,
 
+  /* Bound register.  */
+  RegBND,
+
+  /* Vector 8bit displacement */
+  Vec_Disp8,
+
   /* The last bitfield in i386_operand_type.  */
   OTMax
 };
 
 #define OTNumOfUints \
   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 #define OTNumOfBits \
   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
 #define OTUnused                (OTMax + 1)
 
 typedef union i386_operand_type
 {
   struct
     {
       unsigned int reg8:1;
       unsigned int reg16:1;
       unsigned int reg32:1;
       unsigned int reg64:1;
       unsigned int floatreg:1;
       unsigned int regmmx:1;
       unsigned int regxmm:1;
       unsigned int regymm:1;
+      unsigned int regzmm:1;
+      unsigned int regmask:1;
       unsigned int control:1;
       unsigned int debug:1;
       unsigned int test:1;
       unsigned int sreg2:1;
       unsigned int sreg3:1;
       unsigned int imm1:1;
       unsigned int imm8:1;
       unsigned int imm8s:1;
       unsigned int imm16:1;
       unsigned int imm32:1;
@@ skipping 14 matching lines @@
       unsigned int regmem:1;
       unsigned int mem:1;
       unsigned int byte:1;
       unsigned int word:1;
       unsigned int dword:1;
       unsigned int fword:1;
       unsigned int qword:1;
       unsigned int tbyte:1;
       unsigned int xmmword:1;
       unsigned int ymmword:1;
+      unsigned int zmmword:1;
       unsigned int unspecified:1;
       unsigned int anysize:1;
       unsigned int vec_imm4:1;
+      unsigned int regbnd:1;
+      unsigned int vec_disp8:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif
     } bitfield;
   unsigned int array[OTNumOfUints];
 } i386_operand_type;
 
 typedef struct insn_template
 {
   /* instruction name sans width suffix ("mov" for movl insns) */
@@ skipping 41 matching lines @@
 extern const insn_template i386_optab[];
 
 /* these are for register name --> number & type hash lookup */
 typedef struct
 {
   char *reg_name;
   i386_operand_type reg_type;
   unsigned char reg_flags;
 #define RegRex      0x1  /* Extended register.  */
 #define RegRex64    0x2  /* Extended 8 bit register.  */
+#define RegVRex     0x4  /* Extended vector register.  */
   unsigned char reg_num;
 #define RegRip  ((unsigned char ) ~0)
 #define RegEip  (RegRip - 1)
 /* EIZ and RIZ are fake index registers.  */
 #define RegEiz  (RegEip - 1)
 #define RegRiz  (RegEiz - 1)
 /* FLAT is a fake segment register (Intel mode).  */
 #define RegFlat     ((unsigned char) ~0)
   signed char dw2_regnum[2];
 #define Dw2Inval (-1)
@@ skipping 14 matching lines @@
   unsigned int seg_prefix;
 }
 seg_entry;
 
 extern const seg_entry cs;
 extern const seg_entry ds;
 extern const seg_entry ss;
 extern const seg_entry es;
 extern const seg_entry fs;
 extern const seg_entry gs;