OLD | NEW |
1 /* crx-opc.c -- Table of opcodes for the CRX processor. | 1 /* crx-opc.c -- Table of opcodes for the CRX processor. |
2 Copyright 2004, 2005, 2007, 2012 Free Software Foundation, Inc. | 2 Copyright 2004, 2005, 2007, 2012, 2013 Free Software Foundation, Inc. |
3 Contributed by Tomer Levi NSC, Israel. | 3 Contributed by Tomer Levi NSC, Israel. |
4 Originally written for GAS 2.12 by Tomer Levi. | 4 Originally written for GAS 2.12 by Tomer Levi. |
5 | 5 |
6 This file is part of the GNU opcodes library. | 6 This file is part of the GNU opcodes library. |
7 | 7 |
8 This library is free software; you can redistribute it and/or modify | 8 This library is free software; you can redistribute it and/or modify |
9 it under the terms of the GNU General Public License as published by | 9 it under the terms of the GNU General Public License as published by |
10 the Free Software Foundation; either version 3, or (at your option) | 10 the Free Software Foundation; either version 3, or (at your option) |
11 any later version. | 11 any later version. |
12 | 12 |
(...skipping 523 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
536 {NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, \ | 536 {NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, \ |
537 {{ui4,16}, {regr,0}, {ui16,16}}} | 537 {{ui4,16}, {regr,0}, {ui16,16}}} |
538 | 538 |
539 COPMEM_INST("loadmcr", 0, COP_REG_INS), | 539 COPMEM_INST("loadmcr", 0, COP_REG_INS), |
540 COPMEM_INST("stormcr", 1, COP_REG_INS), | 540 COPMEM_INST("stormcr", 1, COP_REG_INS), |
541 COPMEM_INST("loadmcsr", 2, COPS_REG_INS), | 541 COPMEM_INST("loadmcsr", 2, COPS_REG_INS), |
542 COPMEM_INST("stormcsr", 3, COPS_REG_INS), | 542 COPMEM_INST("stormcsr", 3, COPS_REG_INS), |
543 | 543 |
544 /* CO-processor extensions. */ | 544 /* CO-processor extensions. */ |
545 /* opc12 c4 opc4 ui4 disps9 */ | 545 /* opc12 c4 opc4 ui4 disps9 */ |
546 {"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, | 546 {"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, |
547 {{ui4,8}, {ui4,16}, {disps9,0}}}, | 547 {{ui4,8}, {ui4,16}, {disps9,0}}}, |
548 /* opc12 c4 opc4 ui4 disps25 */ | 548 /* opc12 c4 opc4 ui4 disps25 */ |
549 {"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, | 549 {"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, |
550 {{ui4,8}, {ui4,16}, {disps25,0}}}, | 550 {{ui4,8}, {ui4,16}, {disps25,0}}}, |
551 /* opc12 c4 opc4 cpdo r r */ | 551 /* opc12 c4 opc4 cpdo r r */ |
552 {"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, | 552 {"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, |
553 {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}}}, | 553 {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}}}, |
554 /* opc12 c4 opc4 cpdo r r cpdo16 */ | 554 /* opc12 c4 opc4 cpdo r r cpdo16 */ |
555 {"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, | 555 {"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, |
556 {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}, {ui16,16}}}, | 556 {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}, {ui16,16}}}, |
557 /* esc16 r procreg */ | 557 /* esc16 r procreg */ |
558 {"mtpr", 2, 0x3009, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, | 558 {"mtpr", 2, 0x3009, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, |
559 /* esc16 procreg r */ | 559 /* esc16 procreg r */ |
560 {"mfpr", 2, 0x300A, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, | 560 {"mfpr", 2, 0x300A, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, |
561 | 561 |
562 /* Miscellaneous. */ | 562 /* Miscellaneous. */ |
563 /* opc12 ui4 */ | 563 /* opc12 ui4 */ |
564 {"excp", 1, 0xFFF, 20, NO_TYPE_INS, {{ui4,16}}}, | 564 {"excp", 1, 0xFFF, 20, NO_TYPE_INS, {{ui4,16}}}, |
565 /* opc28 ui4 */ | 565 /* opc28 ui4 */ |
566 {"cinv", 2, 0x3010000, 4, NO_TYPE_INS, {{ui4,0}}}, | 566 {"cinv", 2, 0x3010000, 4, NO_TYPE_INS, {{ui4,0}}}, |
567 | 567 |
568 /* opc9 ui5 ui5 ui5 r r */ | 568 /* opc9 ui5 ui5 ui5 r r */ |
569 {"ram", 2, 0x7C, 23, NO_TYPE_INS, | 569 {"ram", 2, 0x7C, 23, NO_TYPE_INS, |
570 {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, | 570 {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, |
571 {"rim", 2, 0x7D, 23, NO_TYPE_INS, | 571 {"rim", 2, 0x7D, 23, NO_TYPE_INS, |
572 {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, | 572 {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, |
573 | 573 |
574 /* opc9 ui3 r */ | 574 /* opc9 ui3 r */ |
575 {"rotb", 1, 0x1FB, 23, NO_TYPE_INS, {{ui3,20}, {regr,16}}}, | 575 {"rotb", 1, 0x1FB, 23, NO_TYPE_INS, {{ui3,20}, {regr,16}}}, |
576 /* opc8 ui4 r */ | 576 /* opc8 ui4 r */ |
577 {"rotw", 1, 0xB9, 24, NO_TYPE_INS, {{ui4,20}, {regr,16}}}, | 577 {"rotw", 1, 0xB9, 24, NO_TYPE_INS, {{ui4,20}, {regr,16}}}, |
578 /* opc23 ui5 r */ | 578 /* opc23 ui5 r */ |
579 {"rotd", 2, 0x180478, 9, NO_TYPE_INS, {{ui5,4}, {regr,0}}}, | 579 {"rotd", 2, 0x180478, 9, NO_TYPE_INS, {{ui5,4}, {regr,0}}}, |
580 | 580 |
581 {NULL, 0, 0, 0, 0, {{0, 0}}} | 581 {NULL, 0, 0, 0, 0, {{0, 0}}} |
582 }; | 582 }; |
583 | 583 |
584 const int crx_num_opcodes = ARRAY_SIZE (crx_instruction); | 584 const int crx_num_opcodes = ARRAY_SIZE (crx_instruction); |
585 | 585 |
586 /* Macro to build a reg_entry, which have an opcode image : | 586 /* Macro to build a reg_entry, which have an opcode image : |
587 For example : | 587 For example : |
588 REG(u4, 0x84, CRX_U_REGTYPE) | 588 REG(u4, 0x84, CRX_U_REGTYPE) |
589 is interpreted as : | 589 is interpreted as : |
590 {"u4", u4, 0x84, CRX_U_REGTYPE} */ | 590 {"u4", u4, 0x84, CRX_U_REGTYPE} |
591 #define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} | 591 The union initializer (second member) always refers to the first |
| 592 member of the union, so cast NAME to that type to avoid possible |
| 593 compiler warnings when used for non-CRX_R_REGTYPE cases. */ |
| 594 #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} |
592 | 595 |
593 const reg_entry crx_regtab[] = | 596 const reg_entry crx_regtab[] = |
594 { | 597 { |
595 /* Build a general purpose register r<N>. */ | 598 /* Build a general purpose register r<N>. */ |
596 #define REG_R(N) REG(CONCAT2(r,N), N, CRX_R_REGTYPE) | 599 #define REG_R(N) REG(CONCAT2(r,N), N, CRX_R_REGTYPE) |
597 | 600 |
598 REG_R(0), REG_R(1), REG_R(2), REG_R(3), | 601 REG_R(0), REG_R(1), REG_R(2), REG_R(3), |
599 REG_R(4), REG_R(5), REG_R(6), REG_R(7), | 602 REG_R(4), REG_R(5), REG_R(6), REG_R(7), |
600 REG_R(8), REG_R(9), REG_R(10), REG_R(11), | 603 REG_R(8), REG_R(9), REG_R(10), REG_R(11), |
601 REG_R(12), REG_R(13), REG_R(14), REG_R(15), | 604 REG_R(12), REG_R(13), REG_R(14), REG_R(15), |
(...skipping 100 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
702 | 705 |
703 cst4_map[5]=-4 -->> 5 */ | 706 cst4_map[5]=-4 -->> 5 */ |
704 const int cst4_map[] = | 707 const int cst4_map[] = |
705 { | 708 { |
706 0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48 | 709 0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48 |
707 }; | 710 }; |
708 | 711 |
709 const int cst4_maps = ARRAY_SIZE (cst4_map); | 712 const int cst4_maps = ARRAY_SIZE (cst4_map); |
710 | 713 |
711 /* CRX instructions that don't have arguments. */ | 714 /* CRX instructions that don't have arguments. */ |
712 const char* no_op_insn[] = | 715 const char* no_op_insn[] = |
713 { | 716 { |
714 "di", "ei", "eiwait", "nop", "retx", "wait", NULL | 717 "di", "ei", "eiwait", "nop", "retx", "wait", NULL |
715 }; | 718 }; |
OLD | NEW |