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| 1 /* This file is automatically generated by aarch64-gen. Do not edit! */ |
| 2 /* Copyright 2012, 2013 Free Software Foundation, Inc. |
| 3 Contributed by ARM Ltd. |
| 4 |
| 5 This file is part of the GNU opcodes library. |
| 6 |
| 7 This library is free software; you can redistribute it and/or modify |
| 8 it under the terms of the GNU General Public License as published by |
| 9 the Free Software Foundation; either version 3, or (at your option) |
| 10 any later version. |
| 11 |
| 12 It is distributed in the hope that it will be useful, but WITHOUT |
| 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| 15 License for more details. |
| 16 |
| 17 You should have received a copy of the GNU General Public License |
| 18 along with this program; see the file COPYING3. If not, |
| 19 see <http://www.gnu.org/licenses/>. */ |
| 20 |
| 21 #include "sysdep.h" |
| 22 #include "aarch64-opc.h" |
| 23 |
| 24 |
| 25 const struct aarch64_operand aarch64_operands[] = |
| 26 { |
| 27 {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "<none>"}, |
| 28 {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
FLD_Rd}, "an integer register"}, |
| 29 {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
FLD_Rn}, "an integer register"}, |
| 30 {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
FLD_Rm}, "an integer register"}, |
| 31 {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
FLD_Rt}, "an integer register"}, |
| 32 {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rt2}, "an integer register"}, |
| 33 {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
FLD_Rs}, "an integer register"}, |
| 34 {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
FLD_Ra}, "an integer register"}, |
| 35 {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {FLD_Rt}, "an integer register"}, |
| 36 {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OP
D_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"}, |
| 37 {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OP
D_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"}, |
| 38 {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {}, "an integer register with optional extension"}, |
| 39 {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {}, "an integer register with optional shift"}, |
| 40 {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {F
LD_Rd}, "a floating-point register"}, |
| 41 {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {F
LD_Rn}, "a floating-point register"}, |
| 42 {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {F
LD_Rm}, "a floating-point register"}, |
| 43 {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {F
LD_Ra}, "a floating-point register"}, |
| 44 {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {F
LD_Rt}, "a floating-point register"}, |
| 45 {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
FLD_Rt2}, "a floating-point register"}, |
| 46 {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rd}, "a SIMD scalar register"}, |
| 47 {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rn}, "a SIMD scalar register"}, |
| 48 {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rm}, "a SIMD scalar register"}, |
| 49 {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rd}, "a SIMD vector register"}, |
| 50 {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rn}, "a SIMD vector register"}, |
| 51 {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rm}, "a SIMD vector register"}, |
| 52 {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rd}, "the top half of a 128-bit FP/SIMD register"}, |
| 53 {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{FLD_Rn}, "the top half of a 128-bit FP/SIMD register"}, |
| 54 {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_Rd}, "a SIMD vector element"}, |
| 55 {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_Rn}, "a SIMD vector element"}, |
| 56 {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_Rm}, "a SIMD vector element"}, |
| 57 {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRAC
TOR, {FLD_Rn}, "a SIMD vector register list"}, |
| 58 {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRAC
TOR, {}, "a SIMD vector register list"}, |
| 59 {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {}, "a SIMD vector register list"}, |
| 60 {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRAC
TOR, {}, "a SIMD vector element list"}, |
| 61 {AARCH64_OPND_CLASS_CP_REG, "Cn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {F
LD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"}, |
| 62 {AARCH64_OPND_CLASS_CP_REG, "Cm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {F
LD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"}, |
| 63 {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR
, {FLD_imm4}, "an immediate as the index of the least significant byte"}, |
| 64 {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {}, "a left shift amount for an AdvSIMD register"}, |
| 65 {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {}, "a right shift amount for an AdvSIMD register"}, |
| 66 {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {}, "an immediate"}, |
| 67 {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_
EXTRACTOR, {}, "an 8-bit unsigned immediate with optional shift"}, |
| 68 {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EX
TRACTOR, {}, "an 8-bit floating-point constant"}, |
| 69 {AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {}, "an immedi
ate shift amount of 8, 16 or 32"}, |
| 70 {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"}, |
| 71 {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"}, |
| 72 {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_imm8}, "an 8-bit floating-point constant"}, |
| 73 {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {FLD_immr}, "the right rotate amount"}, |
| 74 {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {FLD_imm6}, "the leftmost bit number to be moved from the source"}, |
| 75 {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_imm6}, "the width of the bit-field"}, |
| 76 {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR
, {FLD_imm6}, "an immediate"}, |
| 77 {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {FLD_op1}, "a 3-bit unsigned immediate"}, |
| 78 {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {FLD_op2}, "a 3-bit unsigned immediate"}, |
| 79 {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_CRm}, "a 4-bit unsigned immediate"}, |
| 80 {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"}, |
| 81 {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRA
CTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"}, |
| 82 {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"}, |
| 83 {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, |
| 84 {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}
, |
| 85 {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, |
| 86 {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift
of 12 bits"}, |
| 87 {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {FLD_imm16}, "a 16-bit immediate with optional left shift"}, |
| 88 {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACT
OR, {FLD_scale}, "the number of bits after the binary point in the fixed-point v
alue"}, |
| 89 {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"}, |
| 90 {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}
, "a condition"}, |
| 91 {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {
}, "one of the standard conditions, excluding AL and NV."}, |
| 92 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {F
LD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"}, |
| 93 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | O
PD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative addres
s"}, |
| 94 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | O
PD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative addres
s"}, |
| 95 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER |
OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"}, |
| 96 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | O
PD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative addres
s"}, |
| 97 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {}, "an address with base register (no offset)"}, |
| 98 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {}, "an address with register offset"}, |
| 99 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"}, |
| 100 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"}, |
| 101 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EX
TRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned imme
diate offset"}, |
| 102 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXT
RACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"}
, |
| 103 {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HA
S_EXTRACTOR, {}, "an address with base register (no offset)"}, |
| 104 {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_
EXTRACTOR, {}, "a post-indexed address with immediate or register increment"}, |
| 105 {AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR
, {}, "a system register"}, |
| 106 {AARCH64_OPND_CLASS_SYSTEM, "PSTATEFIELD", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {}, "a PSTATE field name"}, |
| 107 {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_AT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRAC
TOR, {}, "an address translation operation specifier"}, |
| 108 {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRAC
TOR, {}, "a data cache maintenance operation specifier"}, |
| 109 {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRAC
TOR, {}, "an instructin cache maintenance operation specifier"}, |
| 110 {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {}, "a TBL invalidation operation specifier"}, |
| 111 {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTO
R, {}, "a barrier option name"}, |
| 112 {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTR
ACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"}, |
| 113 {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR,
{}, "an prefetch operation specifier"}, |
| 114 {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, |
| 115 }; |
| 116 |
| 117 /* Indexed by an enum aarch64_op enumerator, the value is the offset of |
| 118 the corresponding aarch64_opcode entry in the aarch64_opcode_table. */ |
| 119 |
| 120 static const unsigned op_enum_table [] = |
| 121 { |
| 122 0, |
| 123 660, |
| 124 661, |
| 125 662, |
| 126 665, |
| 127 666, |
| 128 667, |
| 129 668, |
| 130 669, |
| 131 663, |
| 132 664, |
| 133 670, |
| 134 671, |
| 135 693, |
| 136 694, |
| 137 697, |
| 138 703, |
| 139 704, |
| 140 707, |
| 141 709, |
| 142 710, |
| 143 699, |
| 144 700, |
| 145 713, |
| 146 715, |
| 147 753, |
| 148 754, |
| 149 755, |
| 150 756, |
| 151 12, |
| 152 510, |
| 153 511, |
| 154 776, |
| 155 778, |
| 156 780, |
| 157 760, |
| 158 779, |
| 159 777, |
| 160 259, |
| 161 499, |
| 162 509, |
| 163 508, |
| 164 758, |
| 165 505, |
| 166 502, |
| 167 495, |
| 168 494, |
| 169 501, |
| 170 504, |
| 171 506, |
| 172 507, |
| 173 768, |
| 174 526, |
| 175 529, |
| 176 532, |
| 177 527, |
| 178 530, |
| 179 626, |
| 180 160, |
| 181 161, |
| 182 162, |
| 183 163, |
| 184 420, |
| 185 595, |
| 186 314, |
| 187 316, |
| 188 336, |
| 189 338, |
| 190 }; |
| 191 |
| 192 /* Given the opcode enumerator OP, return the pointer to the corresponding |
| 193 opcode entry. */ |
| 194 |
| 195 const aarch64_opcode * |
| 196 aarch64_get_opcode (enum aarch64_op op) |
| 197 { |
| 198 return aarch64_opcode_table + op_enum_table[op]; |
| 199 } |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 124383005:
GDB 7.6.50 (Closed)
Base URL: http://git.chromium.org/native_client/nacl-gdb.git@upstream