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| 1 # Copyright (C) 2008-2012 Free Software Foundation, Inc. | 1 # Copyright (C) 2008-2013 Free Software Foundation, Inc. |
| 2 # | 2 # |
| 3 # This program is free software; you can redistribute it and/or modify | 3 # This program is free software; you can redistribute it and/or modify |
| 4 # it under the terms of the GNU General Public License as published by | 4 # it under the terms of the GNU General Public License as published by |
| 5 # the Free Software Foundation; either version 3 of the License, or | 5 # the Free Software Foundation; either version 3 of the License, or |
| 6 # (at your option) any later version. | 6 # (at your option) any later version. |
| 7 # | 7 # |
| 8 # This program is distributed in the hope that it will be useful, | 8 # This program is distributed in the hope that it will be useful, |
| 9 # but WITHOUT ANY WARRANTY; without even the implied warranty of | 9 # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 # GNU General Public License for more details. | 11 # GNU General Public License for more details. |
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| 121 | 121 |
| 122 for {set i 0} {$i < 32} {incr i 1} { | 122 for {set i 0} {$i < 32} {incr i 1} { |
| 123 gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" | 123 gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" |
| 124 } | 124 } |
| 125 | 125 |
| 126 # Create a core file. We create the core file before the F32~F63/VR0~VR31 test | 126 # Create a core file. We create the core file before the F32~F63/VR0~VR31 test |
| 127 # below because then we'll have more interesting register values to verify | 127 # below because then we'll have more interesting register values to verify |
| 128 # later when loading the core file (i.e., different register values for differen
t | 128 # later when loading the core file (i.e., different register values for differen
t |
| 129 # vector register banks). | 129 # vector register banks). |
| 130 | 130 |
| 131 set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test] | 131 set corefile "${objdir}/${subdir}/vsx-core.test" |
| 132 | 132 set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"] |
| 133 set core_supported 0 | |
| 134 | |
| 135 gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \ | |
| 136 "Save a VSX-enabled corefile" \ | |
| 137 { | |
| 138 -re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" { | |
| 139 pass "Save a VSX-enabled corefile" | |
| 140 global core_supported | |
| 141 set core_supported 1 | |
| 142 } | |
| 143 -re "Can't create a corefile\[\r\n\]+$gdb_prompt $" { | |
| 144 unsupported "Save a VSX-enabled corefile" | |
| 145 global core_supported | |
| 146 set core_supported 0 | |
| 147 } | |
| 148 } | |
| 149 | 133 |
| 150 # Now run the F32~F63/VR0~VR31 tests. | 134 # Now run the F32~F63/VR0~VR31 tests. |
| 151 | 135 |
| 152 # 1: Set F32~F63 registers and check if it reflects on VR0~VR31. | 136 # 1: Set F32~F63 registers and check if it reflects on VR0~VR31. |
| 153 for {set i 32} {$i < 64} {incr i 1} { | 137 for {set i 32} {$i < 64} {incr i 1} { |
| 154 gdb_test_no_output "set \$f$i = 1\.3" | 138 gdb_test_no_output "set \$f$i = 1\.3" |
| 155 } | 139 } |
| 156 | 140 |
| 157 for {set i 0} {$i < 32} {incr i 1} { | 141 for {set i 0} {$i < 32} {incr i 1} { |
| 158 gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (double
word 0)" | 142 gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (double
word 0)" |
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| 177 | 161 |
| 178 if {!$core_supported} { | 162 if {!$core_supported} { |
| 179 return -1 | 163 return -1 |
| 180 } | 164 } |
| 181 | 165 |
| 182 gdb_exit | 166 gdb_exit |
| 183 gdb_start | 167 gdb_start |
| 184 gdb_reinitialize_dir $srcdir/$subdir | 168 gdb_reinitialize_dir $srcdir/$subdir |
| 185 gdb_load ${binfile} | 169 gdb_load ${binfile} |
| 186 | 170 |
| 187 gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \ | 171 set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"] |
| 188 » "re-load generated corefile" \ | 172 if { $core_loaded == -1 } { |
| 189 { | 173 # No use proceeding from here. |
| 190 -re ".* is not a core dump:.*$gdb_prompt $" { | 174 return |
| 191 » fail "re-load generated corefile (bad file format)" | |
| 192 » # No use proceeding from here. | |
| 193 » return; | |
| 194 } | |
| 195 -re ".*: No such file or directory.*$gdb_prompt $" { | |
| 196 » fail "re-load generated corefile (file not found)" | |
| 197 » # No use proceeding from here. | |
| 198 » return; | |
| 199 } | |
| 200 -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" { | |
| 201 » fail "re-load generated corefile (incomplete note section)" | |
| 202 } | |
| 203 -re "Core was generated by .*$gdb_prompt $" { | |
| 204 » pass "re-load generated corefile" | |
| 205 } | |
| 206 -re ".*$gdb_prompt $" { | |
| 207 » fail "re-load generated corefile" | |
| 208 } | |
| 209 timeout { | |
| 210 » fail "re-load generated corefile (timeout)" | |
| 211 } | |
| 212 } | 175 } |
| 213 | 176 |
| 214 for {set i 0} {$i < 32} {incr i 1} { | 177 for {set i 0} {$i < 32} {incr i 1} { |
| 215 gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core f
ile" | 178 gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core f
ile" |
| 216 } | 179 } |
| 217 | 180 |
| 218 for {set i 32} {$i < 64} {incr i 1} { | 181 for {set i 32} {$i < 64} {incr i 1} { |
| 219 gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core f
ile" | 182 gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core f
ile" |
| 220 } | 183 } |
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