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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef VM_CONSTANTS_MIPS_H_ | 5 #ifndef VM_CONSTANTS_MIPS_H_ |
| 6 #define VM_CONSTANTS_MIPS_H_ | 6 #define VM_CONSTANTS_MIPS_H_ |
| 7 | 7 |
| 8 namespace dart { | 8 namespace dart { |
| 9 | 9 |
| 10 enum Register { | 10 enum Register { |
| (...skipping 30 matching lines...) Expand all Loading... | |
| 41 R28 = 28, | 41 R28 = 28, |
| 42 R29 = 29, | 42 R29 = 29, |
| 43 R30 = 30, | 43 R30 = 30, |
| 44 R31 = 31, | 44 R31 = 31, |
| 45 kNumberOfCpuRegisters = 32, | 45 kNumberOfCpuRegisters = 32, |
| 46 kNoRegister = -1, | 46 kNoRegister = -1, |
| 47 | 47 |
| 48 // Register aliases. | 48 // Register aliases. |
| 49 ZR = R0, | 49 ZR = R0, |
| 50 AT = R1, | 50 AT = R1, |
| 51 | |
| 51 V0 = R2, | 52 V0 = R2, |
| 52 V1 = R3, | 53 V1 = R3, |
| 54 | |
| 53 A0 = R4, | 55 A0 = R4, |
| 54 A1 = R5, | 56 A1 = R5, |
| 55 A2 = R6, | 57 A2 = R6, |
| 56 A3 = R7, | 58 A3 = R7, |
| 59 | |
| 57 T0 = R8, | 60 T0 = R8, |
| 58 T1 = R9, | 61 T1 = R9, |
| 59 T2 = R10, | 62 T2 = R10, |
| 60 T3 = R11, | 63 T3 = R11, |
| 61 T4 = R12, | 64 T4 = R12, |
| 62 T5 = R13, | 65 T5 = R13, |
| 63 T6 = R14, | 66 T6 = R14, |
| 64 T7 = R15, | 67 T7 = R15, |
| 68 | |
| 65 S0 = R16, | 69 S0 = R16, |
| 66 S1 = R17, | 70 S1 = R17, |
| 67 S3 = R18, | 71 S2 = R18, |
| 68 S4 = R19, | 72 S3 = R19, |
| 69 S5 = R20, | 73 S4 = R20, |
| 70 S6 = R21, | 74 S5 = R21, |
| 71 S7 = R22, | 75 S6 = R22, |
| 76 S7 = R23, | |
|
Ivan Posva
2013/03/13 21:50:34
Thanks!
| |
| 77 | |
| 72 T8 = R24, | 78 T8 = R24, |
| 73 T9 = R25, | 79 T9 = R25, |
| 80 | |
| 74 K0 = R26, | 81 K0 = R26, |
| 75 K1 = R27, | 82 K1 = R27, |
| 83 | |
| 76 GP = R28, | 84 GP = R28, |
| 77 SP = R29, | 85 SP = R29, |
| 78 FP = R30, | 86 FP = R30, |
| 79 RA = R31, | 87 RA = R31, |
| 80 }; | 88 }; |
| 81 | 89 |
| 82 | 90 |
| 83 // Values for double-precision floating point registers. | 91 // Values for double-precision floating point registers. |
| 84 enum FRegister { | 92 enum FRegister { |
| 85 F0 = 0, | 93 F0 = 0, |
| (...skipping 66 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 152 kRdShift = 11, | 160 kRdShift = 11, |
| 153 kRdBits = 5, | 161 kRdBits = 5, |
| 154 kSaShift = 6, | 162 kSaShift = 6, |
| 155 kSaBits = 5, | 163 kSaBits = 5, |
| 156 kFunctionShift = 0, | 164 kFunctionShift = 0, |
| 157 kFunctionBits = 6, | 165 kFunctionBits = 6, |
| 158 kImmShift = 0, | 166 kImmShift = 0, |
| 159 kImmBits = 16, | 167 kImmBits = 16, |
| 160 kInstrShift = 0, | 168 kInstrShift = 0, |
| 161 kInstrBits = 26, | 169 kInstrBits = 26, |
| 170 kBreakCodeShift = 5, | |
| 171 kBreakCodeBits = 20, | |
| 162 }; | 172 }; |
| 163 | 173 |
| 164 | 174 |
| 165 enum Opcode { | 175 enum Opcode { |
| 166 SPECIAL = 0, | 176 SPECIAL = 0, |
| 167 REGIMM = 1, | 177 REGIMM = 1, |
| 168 J = 2, | 178 J = 2, |
| 169 JAL = 3, | 179 JAL = 3, |
| 170 BEQ = 4, | 180 BEQ = 4, |
| 171 BNE = 5, | 181 BNE = 5, |
| (...skipping 116 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 288 enum { | 298 enum { |
| 289 kInstrSize = 4, | 299 kInstrSize = 4, |
| 290 }; | 300 }; |
| 291 | 301 |
| 292 static const int32_t kBreakPointInstruction = | 302 static const int32_t kBreakPointInstruction = |
| 293 (SPECIAL << kOpcodeShift) | (BREAK << kFunctionShift); | 303 (SPECIAL << kOpcodeShift) | (BREAK << kFunctionShift); |
| 294 static const int32_t kNopInstruction = 0; | 304 static const int32_t kNopInstruction = 0; |
| 295 | 305 |
| 296 // Get the raw instruction bits. | 306 // Get the raw instruction bits. |
| 297 inline int32_t InstructionBits() const { | 307 inline int32_t InstructionBits() const { |
| 298 return reinterpret_cast<int32_t>(this); | 308 return *reinterpret_cast<const int32_t*>(this); |
| 309 } | |
| 310 | |
| 311 // Set the raw instruction bits to value. | |
| 312 inline void SetInstructionBits(int32_t value) { | |
| 313 *reinterpret_cast<int32_t*>(this) = value; | |
| 299 } | 314 } |
| 300 | 315 |
| 301 // Read one particular bit out of the instruction bits. | 316 // Read one particular bit out of the instruction bits. |
| 302 inline int32_t Bit(int nr) const { | 317 inline int32_t Bit(int nr) const { |
| 303 return (InstructionBits() >> nr) & 1; | 318 return (InstructionBits() >> nr) & 1; |
| 304 } | 319 } |
| 305 | 320 |
| 306 // Read a bit field out of the instruction bits. | 321 // Read a bit field out of the instruction bits. |
| 307 inline int32_t Bits(int shift, int count) const { | 322 inline int32_t Bits(int shift, int count) const { |
| 308 return (InstructionBits() >> shift) & ((1 << count) - 1); | 323 return (InstructionBits() >> shift) & ((1 << count) - 1); |
| (...skipping 22 matching lines...) Expand all Loading... | |
| 331 | 346 |
| 332 inline int32_t UImmField() const { | 347 inline int32_t UImmField() const { |
| 333 return Bits(kImmShift, kImmBits); | 348 return Bits(kImmShift, kImmBits); |
| 334 } | 349 } |
| 335 | 350 |
| 336 inline int32_t SImmField() const { | 351 inline int32_t SImmField() const { |
| 337 // Sign-extend the imm field. | 352 // Sign-extend the imm field. |
| 338 return (Bits(kImmShift, kImmBits) << (32 - kImmBits)) >> (32 - kImmBits); | 353 return (Bits(kImmShift, kImmBits) << (32 - kImmBits)) >> (32 - kImmBits); |
| 339 } | 354 } |
| 340 | 355 |
| 356 inline int32_t BreakCodeField() const { | |
| 357 return Bits(kBreakCodeShift, kBreakCodeBits); | |
| 358 } | |
| 359 | |
| 341 inline SpecialFunction FunctionField() const { | 360 inline SpecialFunction FunctionField() const { |
| 342 return static_cast<SpecialFunction>(Bits(kFunctionShift, kFunctionBits)); | 361 return static_cast<SpecialFunction>(Bits(kFunctionShift, kFunctionBits)); |
| 343 } | 362 } |
| 344 | 363 |
| 364 inline bool IsBreakPoint() { | |
| 365 return (OpcodeField() == SPECIAL) && (FunctionField() == BREAK); | |
| 366 } | |
| 367 | |
| 345 // Instructions are read out of a code stream. The only way to get a | 368 // Instructions are read out of a code stream. The only way to get a |
| 346 // reference to an instruction is to convert a pc. There is no way | 369 // reference to an instruction is to convert a pc. There is no way |
| 347 // to allocate or create instances of class Instr. | 370 // to allocate or create instances of class Instr. |
| 348 // Use the At(pc) function to create references to Instr. | 371 // Use the At(pc) function to create references to Instr. |
| 349 static Instr* At(uword pc) { | 372 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } |
| 350 return reinterpret_cast<Instr*>(*reinterpret_cast<int32_t*>(pc)); | |
| 351 } | |
| 352 | 373 |
| 353 private: | 374 private: |
| 354 DISALLOW_ALLOCATION(); | 375 DISALLOW_ALLOCATION(); |
| 355 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 376 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
| 356 }; | 377 }; |
| 357 | 378 |
| 358 } // namespace dart | 379 } // namespace dart |
| 359 | 380 |
| 360 #endif // VM_CONSTANTS_MIPS_H_ | 381 #endif // VM_CONSTANTS_MIPS_H_ |
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