Copies Simulator Debugger from ARM to MIPS.

runtime/vm/disassembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 #include "platform/assert.h"
 
 namespace dart {
 
 class ARMDecoder : public ValueObject {
  public:
   ARMDecoder(char* buffer, size_t buffer_size)
       : buffer_(buffer),
         buffer_size_(buffer_size),
         buffer_pos_(0) {
     buffer_[buffer_pos_] = '\0';
   }
 
   ~ARMDecoder() {}
 
   // Writes one disassembled instruction into 'buffer' (0-terminated).
-  void InstructionDecode(uword pc);
+  // Returns true if the instruction was successfully decoded, false otherwise.
+  bool InstructionDecode(uword pc);
 
  private:
   // Bottleneck functions to print into the out_buffer.
   void Print(const char* str);
 
   // Printing of common values.
   void PrintRegister(int reg);
   void PrintSRegister(int reg);
   void PrintDRegister(int reg);
   void PrintCondition(Instr* instr);
   void PrintShiftRm(Instr* instr);
   void PrintShiftImm(Instr* instr);
   void PrintPU(Instr* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instr* instr, const char* option);
   int FormatSRegister(Instr* instr, const char* option);
   int FormatDRegister(Instr* instr, const char* option);
   int FormatOption(Instr* instr, const char* option);
   void Format(Instr* instr, const char* format);
   void Unknown(Instr* instr);
 
   // Each of these functions decodes one particular instruction type, a 3-bit
   // field in the instruction encoding.
   // Types 0 and 1 are combined as they are largely the same except for the way
   // they interpret the shifter operand.
-  void DecodeType01(Instr* instr);
-  void DecodeType2(Instr* instr);
-  void DecodeType3(Instr* instr);
-  void DecodeType4(Instr* instr);
-  void DecodeType5(Instr* instr);
-  void DecodeType6(Instr* instr);
-  void DecodeType7(Instr* instr);
+  bool DecodeType01(Instr* instr);
+  bool DecodeType2(Instr* instr);
+  bool DecodeType3(Instr* instr);
+  bool DecodeType4(Instr* instr);
+  bool DecodeType5(Instr* instr);
+  bool DecodeType6(Instr* instr);
+  bool DecodeType7(Instr* instr);
 
   // Convenience functions.
   char* get_buffer() const { return buffer_; }
   char* current_position_in_buffer() { return buffer_ + buffer_pos_; }
   size_t remaining_size_in_buffer() { return buffer_size_ - buffer_pos_; }
 
   char* buffer_;  // Decode instructions into this buffer.
   size_t buffer_size_;  // The size of the character buffer.
   size_t buffer_pos_;  // Current character position in buffer.
 
@@ skipping 499 matching lines @@
 }
 
 
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void ARMDecoder::Unknown(Instr* instr) {
   Format(instr, "unknown");
 }
 
 
-void ARMDecoder::DecodeType01(Instr* instr) {
+bool ARMDecoder::DecodeType01(Instr* instr) {
+  bool decoded = true;
+
   if (!instr->IsDataProcessing()) {
     // miscellaneous, multiply, sync primitives, extra loads and stores.
     if (instr->IsMiscellaneous()) {
       switch (instr->Bits(4, 3)) {
         case 1: {
           if (instr->Bits(21, 2) == 0x3) {
             Format(instr, "clz'cond 'rd, 'rm");
           } else if (instr->Bits(21, 2) == 0x1) {
             Format(instr, "bx'cond 'rm");
           } else {
             Unknown(instr);
+            decoded = false;
           }
           break;
         }
         case 3: {
           if (instr->Bits(21, 2) == 0x1) {
             Format(instr, "blx'cond 'rm");
           } else {
             // Could be inlined constant.
             Unknown(instr);
+            decoded = false;
           }
           break;
         }
         case 7: {
           if (instr->Bits(21, 2) == 0x1) {
             Format(instr, "bkpt'cond #'imm12_4");
           } else {
              // Format(instr, "smc'cond");
             Unknown(instr);  // Not used.
+            decoded = false;
           }
           break;
         }
         default: {
           Unknown(instr);  // Not used.
+          decoded = false;
           break;
         }
       }
     } else if (instr->IsMultiplyOrSyncPrimitive()) {
       if (instr->Bit(24) == 0) {
         // multiply instructions
         switch (instr->Bits(21, 3)) {
           case 0: {
             // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
             Format(instr, "mul'cond's 'rn, 'rm, 'rs");
             break;
           }
           case 1: {
             // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
             Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
             break;
           }
           case 3: {
             // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
             Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
             break;
           }
           case 4: {
             // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
             Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs");
             break;
           }
           default: {
             Unknown(instr);  // Not used.
+            decoded = false;
             break;
           }
         }
       } else {
         // synchronization primitives
         switch (instr->Bits(20, 4)) {
           case 8: {
             Format(instr, "strex'cond 'rd, 'rm, ['rn]");
             break;
           }
           case 9: {
             Format(instr, "ldrex'cond 'rd, ['rn]");
             break;
           }
           default: {
             Unknown(instr);  // Not used.
+            decoded = false;
             break;
           }
         }
       }
     } else if (instr->Bit(25) == 1) {
       // 16-bit immediate loads, msr (immediate), and hints
       switch (instr->Bits(20, 5)) {
         case 16: {
           Format(instr, "movw'cond 'rd, #'imm4_12");
           break;
         }
         case 18: {
           if ((instr->Bits(16, 4) == 0) && (instr->Bits(0, 8) == 0)) {
             Format(instr, "nop'cond");
           } else {
             Unknown(instr);  // Not used.
+            decoded = false;
           }
           break;
         }
         case 20: {
           Format(instr, "movt'cond 'rd, #'imm4_12");
           break;
         }
         default: {
           Unknown(instr);  // Not used.
+          decoded = false;
           break;
         }
       }
     } else {
       // extra load/store instructions
       switch (instr->PUField()) {
         case 0: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond'x 'rd2, ['rn], -'rm");
           } else {
@@ skipping 64 matching lines @@
       }
       case RSC: {
         Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
         break;
       }
       case TST: {
         if (instr->HasS()) {
           Format(instr, "tst'cond 'rn, 'shift_op");
         } else {
           Unknown(instr);  // Not used.
+          decoded = false;
         }
         break;
       }
       case TEQ: {
         if (instr->HasS()) {
           Format(instr, "teq'cond 'rn, 'shift_op");
         } else {
           Unknown(instr);  // Not used.
+          decoded = false;
         }
         break;
       }
       case CMP: {
         if (instr->HasS()) {
           Format(instr, "cmp'cond 'rn, 'shift_op");
         } else {
           Unknown(instr);  // Not used.
+          decoded = false;
         }
         break;
       }
       case CMN: {
         if (instr->HasS()) {
           Format(instr, "cmn'cond 'rn, 'shift_op");
         } else {
           Unknown(instr);  // Not used.
+          decoded = false;
         }
         break;
       }
       case ORR: {
         Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
         break;
       }
       case MOV: {
         Format(instr, "mov'cond's 'rd, 'shift_op");
         break;
       }
       case BIC: {
         Format(instr, "bic'cond's 'rd, 'rn, 'shift_op");
         break;
       }
       case MVN: {
         Format(instr, "mvn'cond's 'rd, 'shift_op");
         break;
       }
       default: {
         // The Opcode field is a 4-bit field.
         UNREACHABLE();
         break;
       }
     }
   }
+
+  return decoded;
 }
 
 
-void ARMDecoder::DecodeType2(Instr* instr) {
+bool ARMDecoder::DecodeType2(Instr* instr) {
+  bool decoded = true;
+
   switch (instr->PUField()) {
     case 0: {
       if (instr->HasW()) {
         Unknown(instr);  // Not used.
+        decoded = false;
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
       }
       break;
     }
     case 1: {
       if (instr->HasW()) {
         Unknown(instr);  // Not used.
+        decoded = false;
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
       }
       break;
     }
     case 2: {
       Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
       break;
     }
     case 3: {
       Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
   }
+
+  return decoded;
 }
 
 
-void ARMDecoder::DecodeType3(Instr* instr) {
+bool ARMDecoder::DecodeType3(Instr* instr) {
+  bool decoded = true;
+
   if (instr->IsDivision()) {
     if (instr->Bit(21)) {
       Format(instr, "udiv'cond 'rd, 'rn, 'rm");
     } else {
       Format(instr, "sdiv'cond 'rd, 'rn, 'rm");
     }
-    return;
+    return decoded;
   }
   switch (instr->PUField()) {
     case 0: {
       if (instr->HasW()) {
         Unknown(instr);
+        decoded = false;
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
       }
       break;
     }
     case 1: {
       if (instr->HasW()) {
         Unknown(instr);
+        decoded = false;
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
       }
       break;
     }
     case 2: {
       Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
       break;
     }
     case 3: {
       Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
   }
+
+  return decoded;
 }
 
 
-void ARMDecoder::DecodeType4(Instr* instr) {
+bool ARMDecoder::DecodeType4(Instr* instr) {
+  bool decoded = true;
   if (instr->Bit(22) == 1) {
     Unknown(instr);  // Privileged mode currently not supported.
+    decoded = false;
   } else if (instr->HasL()) {
     Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
   } else {
     Format(instr, "stm'cond'pu 'rn'w, 'rlist");
   }
+  return decoded;
 }
 
 
-void ARMDecoder::DecodeType5(Instr* instr) {
+bool ARMDecoder::DecodeType5(Instr* instr) {
   Format(instr, "b'l'cond 'target ; 'dest");
+  return true;
 }
 
 
-void ARMDecoder::DecodeType6(Instr* instr) {
+bool ARMDecoder::DecodeType6(Instr* instr) {
+  bool decoded = true;
+
   if (instr->IsVFPDoubleTransfer()) {
     if (instr->Bit(8) == 0) {
       if (instr->Bit(20) == 1) {
         Format(instr, "vmovrrs'cond 'rd, 'rn, {'sm, 'sm1}");
       } else {
         Format(instr, "vmovsrr'cond {'sm, 'sm1}, 'rd, 'rn");
       }
     } else {
       if (instr->Bit(20) == 1) {
         Format(instr, "vmovrrd'cond 'rd, 'rn, 'dm");
@@ skipping 40 matching lines @@
       }
     } else {  // vstm
       if (instr->Bit(8)) {  // vstmd
         Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
       } else {  // vstms
         Format(instr, "vstms'cond'pu 'rn'w, 'slist");
       }
     }
   } else {
     Unknown(instr);
+    decoded = false;
   }
+
+  return decoded;
 }
 
 
-void ARMDecoder::DecodeType7(Instr* instr) {
+bool ARMDecoder::DecodeType7(Instr* instr) {
+  bool decoded = true;
+
   if (instr->Bit(24) == 1) {
     Format(instr, "svc'cond #'svc");
     if (instr->SvcField() == kStopMessageSvcCode) {
       const char* message = *reinterpret_cast<const char**>(
           reinterpret_cast<intptr_t>(instr) - Instr::kInstrSize);
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                                  remaining_size_in_buffer(),
                                  " ; \"%s\"",
                                  message);
     }
@@ skipping 13 matching lines @@
               Format(instr, "vmlad'cond 'dd, 'dn, 'dm");
             } else {
               Format(instr, "vmlsd'cond 'dd, 'dn, 'dm");
             }
           }
           break;
         }
         case 1:  // vnmla, vnmls, vnmul
         default: {
           Unknown(instr);
+          decoded = false;
           break;
         }
         case 2: {  // vmul
           if (instr->Bit(8) == 0) {
             Format(instr, "vmuls'cond 'sd, 'sn, 'sm");
           } else {
             Format(instr, "vmuld'cond 'dd, 'dn, 'dm");
           }
           break;
         }
@@ skipping 44 matching lines @@
                 case 3: {  // vabs
                   if (instr->Bit(8) == 0) {
                     Format(instr, "vabss'cond 'sd, 'sm");
                   } else {
                     Format(instr, "vabsd'cond 'dd, 'dm");
                   }
                   break;
                 }
                 default: {
                   Unknown(instr);
+                  decoded = false;
                   break;
                 }
               }
               break;
             }
             case 1: {  // vneg, vsqrt
               switch (instr->Bits(6, 2)) {
                 case 1: {  // vneg
                   if (instr->Bit(8) == 0) {
                     Format(instr, "vnegs'cond 'sd, 'sm");
                   } else {
                     Format(instr, "vnegd'cond 'dd, 'dm");
                   }
                   break;
                 }
                 case 3: {  // vsqrt
                   if (instr->Bit(8) == 0) {
                     Format(instr, "vsqrts'cond 'sd, 'sm");
                   } else {
                     Format(instr, "vsqrtd'cond 'dd, 'dm");
                   }
                   break;
                 }
                 default: {
                   Unknown(instr);
+                  decoded = false;
                   break;
                 }
               }
               break;
             }
             case 4:  // vcmp, vcmpe
             case 5: {  // vcmp #0.0, vcmpe #0.0
               if (instr->Bit(7) == 1) {  // vcmpe
                 Unknown(instr);
+                decoded = false;
               } else {
                 if (instr->Bit(8) == 0) {  // vcmps
                   if (instr->Bit(16) == 0) {
                     Format(instr, "vcmps'cond 'sd, 'sm");
                   } else {
                     Format(instr, "vcmps'cond 'sd, #0.0");
                   }
                 } else {  // vcmpd
                   if (instr->Bit(16) == 0) {
                     Format(instr, "vcmpd'cond 'dd, 'dm");
@@ skipping 26 matching lines @@
                   Format(instr, "vcvtdi'cond 'dd, 'sm");
                 }
               }
               break;
             }
             case 12:
             case 13: {  // vcvt, vcvtr between floating-point and integer
               if (instr->Bit(7) == 0) {
                 // We only support round-to-zero mode
                 Unknown(instr);
+                decoded = false;
                 break;
               }
               if (instr->Bit(8) == 0) {
                 if (instr->Bit(16) == 0) {
                   Format(instr, "vcvtus'cond 'sd, 'sm");
                 } else {
                   Format(instr, "vcvtis'cond 'sd, 'sm");
                 }
               } else {
                 if (instr->Bit(16) == 0) {
                   Format(instr, "vcvtud'cond 'sd, 'dm");
                 } else {
                   Format(instr, "vcvtid'cond 'sd, 'dm");
                 }
               }
               break;
             }
             case 2:  // vcvtb, vcvtt
             case 3:  // vcvtb, vcvtt
             case 9:  // undefined
             case 10:  // vcvt between floating-point and fixed-point
             case 11:  // vcvt between floating-point and fixed-point
             case 14:  // vcvt between floating-point and fixed-point
             case 15:  // vcvt between floating-point and fixed-point
             default: {
               Unknown(instr);
+              decoded = false;
               break;
             }
           }
         }
         break;
       }
     } else {
       // 8, 16, or 32-bit Transfer between ARM Core and VFP
       if ((instr->Bits(21, 3) == 0) && (instr->Bit(8) == 0)) {
         if (instr->Bit(20) == 0) {
           Format(instr, "vmovs'cond 'sn, 'rd");
         } else {
           Format(instr, "vmovr'cond 'rd, 'sn");
         }
       } else if ((instr->Bits(20, 4) == 0xf) && (instr->Bit(8) == 0) &&
                  (instr->Bits(12, 4) == 0xf)) {
         Format(instr, "vmstat'cond");
       } else {
         Unknown(instr);
+        decoded = false;
       }
     }
   } else if (instr->IsMrcIdIsar0()) {
     Format(instr, "mrc'cond p15, 0, 'rd, c0, c2, 0");
   } else {
     Unknown(instr);
+    decoded = false;
   }
+
+  return decoded;
 }
 
 
-void ARMDecoder::InstructionDecode(uword pc) {
-Instr* instr = Instr::At(pc);
+bool ARMDecoder::InstructionDecode(uword pc) {
+  bool decoded = true;
+  Instr* instr = Instr::At(pc);
+
   if (instr->ConditionField() == kSpecialCondition) {
     if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) {
       Format(instr, "clrex");
     } else {
       Unknown(instr);
+      decoded = false;
     }
   } else {
     switch (instr->TypeField()) {
       case 0:
       case 1: {
-        DecodeType01(instr);
+        decoded = DecodeType01(instr);
         break;
       }
       case 2: {
-        DecodeType2(instr);
+        decoded = DecodeType2(instr);
         break;
       }
       case 3: {
-        DecodeType3(instr);
+        decoded = DecodeType3(instr);
         break;
       }
       case 4: {
-        DecodeType4(instr);
+        decoded = DecodeType4(instr);
         break;
       }
       case 5: {
-        DecodeType5(instr);
+        decoded = DecodeType5(instr);
         break;
       }
       case 6: {
-        DecodeType6(instr);
+        decoded = DecodeType6(instr);
         break;
       }
       case 7: {
-        DecodeType7(instr);
+        decoded = DecodeType7(instr);
         break;
       }
       default: {
         // The type field is 3-bits in the ARM encoding.
         UNREACHABLE();
         break;
       }
     }
   }
+
+  return decoded;
 }
 
 
 int Disassembler::DecodeInstruction(char* hex_buffer, intptr_t hex_size,
                                     char* human_buffer, intptr_t human_size,
                                     uword pc) {
   ARMDecoder decoder(human_buffer, human_size);
-  decoder.InstructionDecode(pc);
-  int32_t instruction_bits = Instr::At(pc)->InstructionBits();
-  OS::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
-  return Instr::kInstrSize;
+  if (decoder.InstructionDecode(pc)) {
+    int32_t instruction_bits = Instr::At(pc)->InstructionBits();
+    OS::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
+    return Instr::kInstrSize;
+  } else {
+    return -Instr::kInstrSize;

[regis, 2013/03/12 20:53:19]

Did you mean to return 0? I am worried about returning a negative value or even
0, as will get stuck in a never ending decoding loop.

+  }
 }
 
 
-void Disassembler::Disassemble(uword start,
+bool Disassembler::Disassemble(uword start,
                                uword end,
                                DisassemblyFormatter* formatter,
                                const Code::Comments& comments) {
   ASSERT(formatter != NULL);
+  bool success = true;
   char hex_buffer[kHexadecimalBufferSize];  // Instruction in hexadecimal form.
   char human_buffer[kUserReadableBufferSize];  // Human-readable instruction.
   uword pc = start;
   intptr_t comment_finger = 0;
   while (pc < end) {
     const intptr_t offset = pc - start;
     while (comment_finger < comments.Length() &&
            comments.PCOffsetAt(comment_finger) <= offset) {
       formatter->Print(
           "        ;; %s\n",
           String::Handle(comments.CommentAt(comment_finger)).ToCString());
       comment_finger++;
     }
     int instruction_length = DecodeInstruction(hex_buffer,
                                                sizeof(hex_buffer),
                                                human_buffer,
                                                sizeof(human_buffer),
                                                pc);
-    formatter->ConsumeInstruction(hex_buffer,
-                                  sizeof(hex_buffer),
-                                  human_buffer,
-                                  sizeof(human_buffer),
-                                  pc);
-    pc += instruction_length;
+    if (instruction_length > 0) {
+      formatter->ConsumeInstruction(hex_buffer,
+                                    sizeof(hex_buffer),
+                                    human_buffer,
+                                    sizeof(human_buffer),
+                                    pc);
+      pc += instruction_length;
+    } else {
+      ASSERT(instruction_length < 0);
+      success = false;
+      pc += (-instruction_length);

[regis, 2013/03/12 20:53:19]

I see. You encode success/failure in the returned size. It would be cleaner to
change DecodeInstruction to also return a bool and add a decoded_size reference
parameter.

+    }
   }
+
+  return success;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM